# US 2022/0037286 A1 · Semiconductor packages including dam patterns and methods for manufacturing the same

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- Number: US 2022/0037286 A1
- Document ID: US20220037286A1
- Status: Published application
- Kind: A1
- Application number: 17/203,555
- Filed: 2021-03-16
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Shin Young PARK; Dong Hyun KIM
- Web page: https://patentgrep.com/patent/US20220037286A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/0198: {batch processes}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.

## Claims

### Claim 1

A semiconductor package comprising:
a package substrate with vent holes formed therethrough;
semiconductor chips disposed on the package substrate; and
a molding layer including an upper molding portion that encapsulates the semiconductor chips, and a lower molding portion that is connected to the upper molding portion through the vent holes,
wherein the package substrate includes:
a substrate body including a plurality of unit regions with the vent holes disposed therethrough;
ball lands disposed in each of the unit regions of the substrate body; and
first and second dam patterns that are spaced apart from the ball lands of the substrate body, extending across the unit regions and further extending into edge regions of the substrate body, which is outside of the unit regions.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the lower molding portion extends across the unit regions to partially overlap with spaces between the first and second dam patterns and further extends into the edge regions of the substrate body, which is outside of the unit regions.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the vent holes are disposed between the first and second dam patterns of the package substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the first and second dam patterns include linear patterns that extend while facing each other.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising third dam patterns that connect edge portions of the first and second dam patterns.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the third dam patterns are disposed in the edge regions of the substrate body.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the package substrate further includes a dielectric layer that extends to cover the substrate body, the first and second dam patterns being covered and some portions of the ball lands being opened by the dielectric layer.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein the dielectric layer includes a solder resist material.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the first and second dam patterns and the ball lands include substantially the same metal material.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein the first and second dam patterns and the ball lands include copper (Cu).

### Claim 11 (depends on 1)

The semiconductor package of claim 1,
wherein the substrate body includes first and second surfaces that are on opposite sides of each other,
wherein the semiconductor chips are disposed on the first surface, and
wherein the ball lands and the first and second dam patterns are disposed under the second surface.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein the edge region of the substrate body includes a portion between an outermost unit region, among the unit regions, and an edge of the substrate body.

### Claim 13 (depends on 1)

The semiconductor package of claim 1, wherein the vent holes overlap with the semiconductor chips.

### Claim 14

A semiconductor package comprising:
a package substrate with vent holes formed therethrough;
semiconductor chips disposed on the package substrate; and
a molding layer including an upper molding portion that encapsulates the semiconductor chips, and a lower molding portion that is connected to the upper molding portion through the vent holes,
wherein the package substrate includes:
a substrate body including first and second edges that are on opposite sides of each other and a surface between the first and second edges;
ball lands disposed on the surface of the substrate body; and
first and second dam patterns spaced apart from the ball lands, extending to the first and second edges across the surface.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the lower molding portion extends to the first and second edges across the surface of the substrate body and across the unit regions to partially overlap with spaces between the first and second dam patterns.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein the vent holes are disposed between the first and second dam patterns of the package substrate.

### Claim 17 (depends on 15)

The semiconductor package of claim 15, wherein the first and second dam patterns include linear patterns that extend to face each other.

### Claim 18 (depends on 15)

The semiconductor package of claim 15, wherein the package substrate further includes a dielectric layer that extends to cover the surface of the substrate body, the first and second dam patterns being covered and some portions of the ball lands being opened by the dielectric layer.

### Claim 19 (depends on 15)

The semiconductor package of claim 15, wherein the first and second dam patterns and the ball lands include substantially the same metal material.

### Claim 20 (depends on 15)

The semiconductor package of claim 15, wherein the vent holes overlap with the semiconductor chips.

### Claim 21

A method of manufacturing a semiconductor package, the method comprising:
disposing semiconductor chips on a package substrate with vent holes therethrough, the package substrate including a substrate body with a plurality of unit regions, ball lands disposed in the unit regions of the substrate body, first and second dam patterns that are spaced apart from the ball lands of the substrate body, extends across the unit regions, and further extends into edge regions of the substrate body outside the unit regions, and a dielectric layer extending to cover the substrate to cover the first and second dam patterns and to open some portions of the ball lands;
loading the package substrate in a mold chase, including an upper mold that provides an upper cavity in which the semiconductor chips are to be located and a lower mold that provides a lower cavity to which the vent holes are connected; and
molding a molding layer into an upper molding portion by filling the upper cavity and a lower molding portion by filling the lower cavity while being connected to the upper molding portion through the vent holes,
wherein the lower mold includes sides of lower mold with upper ends overlapping with the first and second dam patterns of the package substrate and contacting a surface of the dielectric layer to close the lower cavity.

### Claim 22 (depends on 21)

The method of claim 21, wherein the lower molding portion fills the lower cavity to be molded in a shape that partially overlaps with spaces between the first and second dam patterns of the substrate body, extends across the unit regions, and further extends into the edge regions of the substrate body, which is outside of the unit regions.

### Claim 23 (depends on 21)

The method of claim 21, wherein the vent holes are disposed between the first and second dam patterns.

### Claim 24 (depends on 21)

The method of claim 21, wherein the first and second dam patterns include linear patterns that extend to face each other.

### Claim 25 (depends on 21)

The method of claim 21,
the semiconductor package further includes third dam patterns that connect edge portions of the first and second dam patterns to each other, and
wherein the upper ends of the sides of lower mold further extend to overlap with the third dam patterns.

### Claim 26 (depends on 25)

The method of claim 25, wherein the third dam patterns are disposed in the edge portions of the substrate body.

### Claim 27 (depends on 21)

The method of claim 21, wherein the dielectric layer includes a solder resist material.

### Claim 28 (depends on 21)

The method of claim 21, wherein the first and second dam patterns and the ball lands include substantially the same metal material.

### Claim 29 (depends on 28)

The method of claim 28, wherein the first and second dam patterns and the ball lands include copper (Cu).

### Claim 30 (depends on 21)

The method of claim 21,
wherein the substrate body includes first and second surfaces that are on opposite sides of each other,
wherein the semiconductor chips are disposed on the first surface, and
wherein the ball lands and the first and second dam patterns are disposed under the second surface.

### Claim 31 (depends on 21)

The method of claim 21, wherein the edge region of the substrate body includes a portion between an outermost unit region among the unit regions and an edge of the substrate body.

### Claim 32 (depends on 21)

The method of claim 21, wherein the vent holes overlap with the semiconductor chips.

### Claim 33

A semiconductor package comprising:
a package substrate with vent holes formed therethrough;
semiconductor chips disposed on the package substrate;
wherein the package substrate includes:
a substrate body including a plurality of unit regions with the vent holes disposed therethrough;
first and second dam patterns extending across the unit regions and further extending into edge regions of the substrate body, which is outside of the unit regions;
a dielectric layer covering the first and second dam patterns; and
a lower mold formed on the dielectric layer to be aligned with the first and second dam patterns,
wherein the first and second dam patterns are formed of a harder material than the dielectric layer.