# US 2022/0037282 A1 · Techniques for forming semiconductor device packages and related packages, intermediate products, and methods

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- Number: US 2022/0037282 A1
- Document ID: US20220037282A1
- Status: Published application
- Kind: A1
- Application number: 17/451,693
- Filed: 2021-10-21
- Published: 2022-02-03
- Earliest claimed: 2019-09-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Po Chih Yang; Yu Jen Chen; Po Chen Kuo; Shih Wei Liang
- Web page: https://patentgrep.com/patent/US20220037282A1

## CPC

- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 72/016: {of strap connectors}
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/07355: {changes in materials}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/357: {Multiple die-attach connectors having different materials}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

## Claims

### Claim 1

A semiconductor device package, comprising:
a first semiconductor device over a substrate;
a second semiconductor device over the first semiconductor device, an active surface of the second semiconductor device facing away from the substrate;
at least one conductor extending from a bond pad of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to a conductive pad of the substrate, the at least one conductor in contact with the bond pad and the conductive pad and a dielectric material interposed between the at least one conductor and the first semiconductor device and between the at least one conductor and the second semiconductor device, a lateral side surface of the first semiconductor device intersecting the conductive pad; and
an encapsulant distinct from the dielectric material extending over the at least one conductor and exposed surfaces of the first semiconductor device, the second semiconductor device, and an upper surface of the substrate.

### Claim 2 (depends on 1)

The semiconductor device package of claim 1, wherein the semiconductor device package lacks wire bonds extending from the second semiconductor device to the substrate.

### Claim 3 (depends on 1)

The semiconductor device package of claim 1, wherein the at least one conductor comprises a seed material and an electrically conductive material plated on the seed material.

### Claim 4 (depends on 1)

The semiconductor device package of claim 1, wherein a space between the at least one conductor and the first semiconductor device and between the at least one conductor and the second semiconductor device lacks the encapsulant in the space.

### Claim 5 (depends on 1)

The semiconductor device package of claim 1, wherein the first semiconductor device is configured as a logic controller and the second semiconductor device is configured as a memory device.

### Claim 6 (depends on 1)

The semiconductor device package of claim 1, wherein the first semiconductor device is affixed to the substrate with another active surface of the first semiconductor device facing the substrate.

### Claim 7 (depends on 6)

The semiconductor device package of claim 6, wherein other bond pads of the first semiconductor device are located adjacent to a geometric centerline of the first semiconductor device.

### Claim 8 (depends on 7)

The semiconductor device package of claim 7, further comprising an electrically conductive material comprising traces interposed between the first semiconductor device and the substrate laterally operably coupled to the other bond pads of the first semiconductor device and to routing members of the substrate.

### Claim 9 (depends on 1)

The semiconductor device package of claim 1, wherein a first lateral distance between the bond pad of the second semiconductor device and another lateral side surface of the second semiconductor device is between about 10% and about 25% of a second lateral distance between the bond pad and a geometric center of the second semiconductor device.

### Claim 10 (depends on 1)

The semiconductor device package of claim 1, wherein at least a portion of the first semiconductor device extends laterally beyond a periphery of the second semiconductor device on at least another lateral side of the second semiconductor device.

### Claim 11 (depends on 1)

The semiconductor device package of claim 1, further comprising a die-attach film or a molded underfill interposed between the first semiconductor device and the second semiconductor device.

### Claim 12 (depends on 1)

The semiconductor device package of claim 1, wherein the conductive pad of the substrate is connected to a routing member extending from a first major surface of the substrate to a second major surface on a side of the substrate opposite the first semiconductor device.

### Claim 13 (depends on 1)

The semiconductor device package of claim 1, further comprising at least another conductor extending from another bond pad of the second semiconductor device, along other surfaces of the second semiconductor device, first semiconductor device, and substrate to another conductive pad of the substrate, the at least another conductor located on a lateral side of the second semiconductor device opposite the at least one conductor.

### Claim 14 (depends on 13)

The semiconductor device package of claim 13, wherein a second lateral footprint of the second semiconductor device is smaller than a first lateral footprint of the first semiconductor device, as measured in a direction intersecting the at least one conductor and the at least another conductor.

### Claim 15 (depends on 14)

The semiconductor device package of claim 14, wherein the second semiconductor device is at least substantially centered over the first semiconductor device.

### Claim 16 (depends on 13)

The semiconductor device package of claim 13, wherein the semiconductor device package is at least substantially symmetrical across a plane bisecting the semiconductor device package between the at least one conductor and the at least another conductor.

### Claim 17 (depends on 1)

The semiconductor device package of claim 1, wherein the at least one conductor extends from the conductive pad, in a direction away from the substrate along the lateral side surface of the first semiconductor device, in a direction toward a lateral center of the semiconductor device package along an inactive surface of the first semiconductor device, in a direction away from the first semiconductor device along another lateral side surface of the second semiconductor device, and in the direction toward the lateral center of the semiconductor device package along the active surface of the second semiconductor device.

### Claim 18

An intermediate product in a method of making a semiconductor device package, comprising:
a first semiconductor device over a substrate;
a second semiconductor device over the first semiconductor device, an active surface of the second semiconductor device facing away from the substrate; and
at least one conductor extending from a bond pad of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to a conductive pad of the substrate, the at least one conductor in contact with the bond pad and the conductive pad and a dielectric material interposed between the at least one conductor and the first semiconductor device and between the at least one conductor and the second semiconductor device, a lateral side surface of the first semiconductor device intersecting the conductive pad.

### Claim 19 (depends on 18)

The intermediate product of claim 18, wherein a width and a thickness of the at least one conductor is greater than a diameter of a wire bond.

### Claim 20 (depends on 18)

The intermediate product of claim 18, wherein an active surface of the first semiconductor device faces the substrate.