# US 2022/0037280 A1 · Multi-layer semiconductor package with stacked passive components

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- Number: US 2022/0037280 A1
- Document ID: US20220037280A1
- Status: Published application
- Kind: A1
- Application number: 16/941,818
- Filed: 2020-07-29
- Published: 2022-02-03
- Earliest claimed: 2020-07-29
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Yiqi Tang; Naweed Anjum; Liang Wan; Michael Gerald Amaro
- Web page: https://patentgrep.com/patent/US20220037280A1

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/464: {Additional interconnections in combination with leadframes}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 90/811: {Multiple chips on leadframes}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/073: {of die-attach connectors}
- H10W 90/00: Package configurations
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

## Claims

### Claim 1

A semiconductor package, comprising:
a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate;
a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and
a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the inductor is exposed on an outer surface of the semiconductor package.

### Claim 3 (depends on 1)

The semiconductor package of claim 1,
wherein the dielectric substrate is a first dielectric substrate, the second layer further including a second dielectric substrate,
wherein the passive component is embedded in the second dielectric substrate, and
wherein the second set of metal pillars extend through the second dielectric substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,
wherein the dielectric substrate forms vias over the bond pads, and
wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising a base layer including a leadframe, wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to elements of the leadframe.

### Claim 6 (depends on 5)

The semiconductor package of claim 5, wherein the dielectric substrate is a first dielectric substrate, the base layer further including a second dielectric substrate filling gaps between the elements of the leadframe.

### Claim 7 (depends on 5)

The semiconductor package of claim 5,
wherein the metal trace is a first metal trace,
wherein the first layer further includes a second metal trace over the leadframe, and
wherein the semiconductor die and the first set of metal pillars are adjacent to the second metal trace.

### Claim 8 (depends on 5)

The semiconductor package of claim 5,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the semiconductor die is in a flip-chip arrangement with the bond pads electrically coupled to the leadframe.

### Claim 9 (depends on 5)

The semiconductor package of claim 5,
wherein the leadframe includes die attach pad,
wherein an inactive surface of the semiconductor die is bonded to the die attach pad,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the bond pads are electrically coupled to the metal trace.

### Claim 10

A semiconductor package comprising:
a base layer including a leadframe and a base layer dielectric substrate filling gaps between elements of the leadframe;
a first layer including a semiconductor die embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,
wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the elements of the leadframe;
a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and
a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,
wherein the inductor is exposed on an outer surface of the semiconductor package.

### Claim 11 (depends on 10)

The semiconductor package of claim 10,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,
wherein the second dielectric substrate forms vias over the bond pads, and
wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

### Claim 12 (depends on 10)

The semiconductor package of claim 10,
wherein the leadframe includes die attach pad,
wherein an inactive surface of semiconductor die is bonded to the die attach pad,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the bond pads are electrically coupled to the metal trace.

### Claim 13 (depends on 10)

The semiconductor package of claim 10,
wherein the second layer further includes a third dielectric substrate,
wherein the passive component is embedded in the third dielectric substrate, and
wherein the second set of metal pillars extend through the third dielectric substrate.

### Claim at position 14

14-22. (canceled)

### Claim 23

A method of making a semiconductor package, comprising:
providing a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate;
providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and
providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

### Claim 24 (depends on 23)

The method of claim 23, wherein the inductor is exposed on an outer surface of the semiconductor package.

### Claim 25 (depends on 23)

The method of claim 23,
wherein the dielectric substrate is a first dielectric substrate, the second layer further including a second dielectric substrate,
wherein the passive component is embedded in the second dielectric substrate, and
wherein the second set of metal pillars extend through the second dielectric substrate.

### Claim 26 (depends on 23)

The method of claim 23,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,
wherein the dielectric substrate forms vias over the bond pads, and
wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

### Claim 27 (depends on 23)

The method of claim 23, further comprising providing a base layer including a leadframe, wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to elements of the leadframe.

### Claim 28 (depends on 27)

The method of claim 27, wherein the dielectric substrate is a first dielectric substrate, the base layer further including a second dielectric substrate filling gaps between the elements of the leadframe.

### Claim 29 (depends on 27)

The method of claim 27,
wherein the metal trace is a first metal trace,
wherein the first layer further includes a second metal trace over the leadframe, and
wherein the semiconductor die and the first set of metal pillars are adjacent to the second metal trace.

### Claim 30 (depends on 27)

The method of claim 27,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the semiconductor die is in a flip-chip arrangement with the bond pads electrically coupled to the leadframe.

### Claim 31 (depends on 27)

The method of claim 27,
wherein the leadframe includes die attach pad,
wherein an inactive surface of the semiconductor die is bonded to the die attach pad,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the bond pads are electrically coupled to the metal trace.

### Claim 32

A method of making a semiconductor package comprising:
providing a base layer including a leadframe and a base layer dielectric substrate filling gaps between elements of the leadframe;
providing a first layer including a semiconductor die embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,
wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the elements of the leadframe;
providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and
providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,
wherein the inductor is exposed on an outer surface of the semiconductor package.

### Claim 33 (depends on 32)

The method of claim 32,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,
wherein the second dielectric substrate forms vias over the bond pads, and
wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

### Claim 34 (depends on 32)

The method of claim 32,
wherein the leadframe includes die attach pad,
wherein an inactive surface of semiconductor die is bonded to the die attach pad,
wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and
wherein the bond pads are electrically coupled to the metal trace.

### Claim 35 (depends on 32)

The method of claim 32,
wherein the second layer further includes a third dielectric substrate,
wherein the passive component is embedded in the third dielectric substrate, and
wherein the second set of metal pillars extend through the third dielectric substrate.