# US 2022/0037259 A1 · Fan-out semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0037259 A1 - Document ID: US20220037259A1 - Status: Published application - Kind: A1 - Application number: 17/194,438 - Filed: 2021-03-08 - Published: 2022-02-03 - Earliest claimed: 2020-07-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Myung Sam KANG; Ki Ju LEE; Young Chan KO; Jeong Seok KIM; Bong Ju CHO - Web page: https://patentgrep.com/patent/US20220037259A1 ## CPC - H10W 70/614: {the multiple chips being integrally enclosed} - H10P 72/74: {using temporarily an auxiliary support} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/0198: {batch processes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer. ## Claims ### Claim 1 A fan-out semiconductor package, comprising: a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein: the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer. ### Claim 2 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein: the first redistribution layer includes an insulating layer, a second line wiring, and a second via that penetrates the insulating layer and is electrically connected to the second line wiring, and the second via is connected to the interconnector. ### Claim 3 (depends on 2) The fan-out semiconductor package as claimed in claim 2, wherein an interface between the second via and the interconnector is a curved surface. ### Claim 4 (depends on 2) The fan-out semiconductor package as claimed in claim 2, wherein an interface between the second via and the interconnector, and an interface between the insulating layer and the interconnector are located on the same plane. ### Claim 5 (depends on 2) The fan-out semiconductor package as claimed in claim 2, wherein: the interconnector is electrically connected to the first line wiring through the first via and electrically connected to the second line wiring through the second via, and the first semiconductor chip is electrically connected to the first line wiring. ### Claim 6 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein interface between the first via and the interconnector is a curved surface. ### Claim 7 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein a diameter of the interconnector is smaller than a thickness of the molded layer. ### Claim 8 (depends on 7) The fan-out semiconductor package as claimed in claim 7, wherein a sum of a thickness of the first via and the diameter of the interconnector is greater than the thickness of the molded layer. ### Claim 9 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein: the interconnector further includes a coating layer thereon, the coating layer coating the metal ball, and the coating layer is in contact with the first via. ### Claim 10 (depends on 9) The fan-out semiconductor package as claimed in claim 9, wherein the coating layer includes a solder. ### Claim 11 (depends on 1) The fan-out semiconductor package as claimed in claim 1, further comprising an electromagnetic wave shielding film that extends along an upper surface and side walls of the first semiconductor chip and is spaced apart from the interconnector. ### Claim 12 (depends on 11) The fan-out semiconductor package as claimed in claim 11, further comprising a heat slug that extends along an upper surface of the electromagnetic shielding film. ### Claim 13 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein a diameter of the interconnector is substantially the same as a thickness of the first semiconductor chip. ### Claim 14 (depends on 13) The fan-out semiconductor package as claimed in claim 13, wherein an upper surface of the first semiconductor chip is in contact with the second redistribution layer. ### Claim 15 (depends on 1) The fan-out semiconductor package as claimed in claim 1, further comprising a semiconductor package on the second redistribution layer and electrically connected to the first line wiring of the second redistribution layer, wherein: the semiconductor package includes a second semiconductor chip different from the first semiconductor chip, and the second semiconductor chip is electrically connected to the first semiconductor chip through the second redistribution layer, the interconnector, and the first redistribution layer. ### Claim 16 (depends on 15) The fan-out semiconductor package as claimed in claim 15, further comprising a heat slug that extends along an upper surface of the semiconductor package. ### Claim 17 (depends on 1) The fan-out semiconductor package as claimed in claim 1, wherein the fan-out semiconductor package is a fan-out panel level package. ### Claim 18 A fan-out semiconductor package, comprising: a molded layer including first and second surfaces opposite to each other; an interconnector in the molded layer, the interconnector including a metal ball; a semiconductor chip in the molded layer and spaced apart from the interconnector; a first redistribution layer including a first line wiring and a first via on the first surface of the molded layer; and a second redistribution layer on the second surface of the molded layer and including a second line wiring and a second via, wherein the interconnector is between the first via and the second via and connected to the first via and the second via. ### Claim 19 (depends on 18) The fan-out semiconductor package as claimed in claim 18, wherein a part of the first via is in the molded layer. ### Claim 20 A fan-out semiconductor package, comprising: a first redistribution layer including a first line wiring and a first via connected to the first line wiring; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and covering side surfaces of the first semiconductor chip; a second redistribution layer on the molded layer, the second redistribution layer including a second line wiring and a second via connected to the second line wiring; and a semiconductor package that includes a second semiconductor chip on the second redistribution layer and connected to the second line wiring, wherein: the interconnector includes a metal ball, the first via is in contact with the interconnector, the second via is in contact with the interconnector, a part of the second via is inside the molded layer, and the first semiconductor chip is electrically connected to the second semiconductor chip through the first line wiring, the first via, the interconnector, the second via, and the second line wiring.