# US 2022/0037166 A1 · Semiconductor package and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0037166 A1 - Document ID: US20220037166A1 - Status: Published application - Kind: A1 - Application number: 17/161,818 - Filed: 2021-01-29 - Published: 2022-02-03 - Earliest claimed: 2020-07-29 - Assignees: Chipbond Technology Corporation - Applicants: Chipbond Technology Corporation - Inventors: Chih-Ming Kuo; Lung-Hua Ho; You-Ming Hsu; Fei-Jain Wu - Web page: https://patentgrep.com/patent/US20220037166A1 ## CPC - H10W 74/014: {using batch processing} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/74: {using temporarily an auxiliary support} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 74/01: Manufacture or treatment - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/111: {the semiconductor body being completely enclosed} - H10P 72/7418: {of passive members, e.g. a chip mounting substrate} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/10: characterised by their shape or disposition - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation. ## Claims ### Claim 1 A method of fabricating semiconductor package comprising steps of: disposing a plurality of semiconductor devices on a carrier; forming an encapsulation on the carrier, the encapsulation is configured to cover the plurality of semiconductor devices and includes a recession, wherein the recession includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation. ### Claim 2 (depends on 1) The method in accordance with claim 1, wherein the plurality of semiconductor devices are embedded in the recessed portion of the recession. ### Claim 3 (depends on 2) The method in accordance with claim 2, wherein the plurality of the semiconductor devices are not embedded in the strengthening portion. ### Claim 4 (depends on 1) The method in accordance with claim 1, wherein a first distance exists between a recession bottom of the recessed portion and a bottom surface of the encapsulation and is less than or equal to 500 μm, and a second distance exists between a top surface of the strengthening portion and the bottom surface of the encapsulation and is more than or equal to 600 μm. ### Claim 5 (depends on 1) The method in accordance with claim 1, wherein a plurality of stiffening ribs are disposed on a recession bottom of the recession. ### Claim 6 (depends on 1) The method in accordance with claim 1 further comprising steps of: removing the carrier; adhering the encapsulation to a dicing tape; and dicing the encapsulation into a plurality of semiconductor package elements. ### Claim 7 (depends on 1) The method in accordance with claim 1, wherein each of the plurality of semiconductor devices includes a chip having an active surface and a back surface, the active surface is configured to contact with the carrier and the back surface is covered by the encapsulation, there are a plurality of pads on the active surface, wherein a redistribution layer is disposed on the active surface after removing the carrier and is electrically connected to the plurality of pads, and a plurality of connectors are disposed on the redistribution layer, and each of the plurality of connectors is electrically connected to each of the plurality of pads via the redistribution layer. ### Claim 8 (depends on 7) The method in accordance with claim 7, wherein the step of forming the encapsulation on the carrier includes sub-steps of: providing a mold having a mold cavity; placing the carrier and the plurality of semiconductor devices thereon in the mold cavity of the mold; putting an encapsulating material into the mold cavity; and curing the encapsulating material to form the encapsulation, wherein the mold cavity has a concave shape and configured to form the encapsulation having the recession directly. ### Claim 9 (depends on 1) The method in accordance with claim 1, wherein the step of forming the encapsulation on the carrier includes sub-steps of: providing a mold having a mold cavity; placing the carrier and the plurality of semiconductor devices thereon in the mold cavity of the mold; putting an encapsulating material into the mold cavity; and curing the encapsulating material to form the encapsulation, wherein the mold cavity has a concave shape and configured to form the encapsulation having the recession directly. ### Claim 10 (depends on 1) The method in accordance with claim 1, wherein each of the plurality of semiconductor devices includes a chip having an active surface and a back surface, the back surface is configured to contact with the carrier, there are a plurality of pads and a plurality of bumps on the active surface, each of the plurality of bumps is electrically connected to each of the plurality of pads, wherein a bottom surface of the encapsulation is configured to be grinder to expose the plurality of bumps on the bottom surface after forming the encapsulation on the carrier, a redistribution layer is disposed on the bottom surface and electrically connected to the plurality of bumps, a plurality of connectors are disposed on the redistribution layer, and each of the plurality of connectors is electrically connected to each of the plurality of bumps via the redistribution layer. ### Claim 11 (depends on 1) The method in accordance with claim 1, wherein each of the plurality of semiconductor devices includes a chip and a redistribution layer, a first surface of the redistribution layer is configured to contact with the carrier, the chip having an active surface and a back surface is mounted on a second surface of the redistribution layer, there are a plurality of pads and a plurality of bumps on the active surface, the plurality of bumps are electrically connected to the plurality of pads and the redistribution layer, each of the plurality of pads is electrically connected to the redistribution layer via each of the plurality of bumps, wherein the carrier is configured to be removed and a plurality of connectors are disposed on the first surface of the redistribution layer after forming the encapsulation on the carrier, and each of the plurality of connectors is electrically connected to each of the plurality of bumps via the redistribution layer. ### Claim 12 (depends on 11) The method in accordance with claim 11, wherein the step of forming the encapsulation on the carrier includes sub-steps of: providing a mold having a mold cavity; placing the carrier and the plurality of semiconductor devices thereon in the mold cavity of the mold; putting an encapsulating material into the mold cavity; curing the encapsulating material to form the encapsulation; and grinding the encapsulation to form the recession. ### Claim 13 (depends on 1) The method in accordance with claim 1, wherein the step of forming the encapsulation on the carrier includes sub-steps of: providing a mold having a mold cavity; placing the carrier and the plurality of semiconductor devices thereon in the mold cavity of the mold; putting an encapsulating material into the mold cavity; curing the encapsulating material to form the encapsulation; and grinding the encapsulation to form the recession. ### Claim 14 A semiconductor package comprising: a carrier; a plurality of semiconductor devices disposed on the carrier; and an encapsulation disposed on the carrier and configured to cover the plurality of semiconductor devices, the encapsulation includes a recession, wherein the recession includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion. ### Claim 15 (depends on 14) The semiconductor package in accordance with claim 14, wherein the plurality of semiconductor devices are embedded in the recessed portion of the recession. ### Claim 16 (depends on 15) The semiconductor package in accordance with claim 15, wherein the plurality of the semiconductor devices are not embedded in the strengthening portion. ### Claim 17 (depends on 14) The semiconductor package in accordance with claim 14, wherein a first distance exists between a recession bottom of the recessed portion and a bottom surface of the encapsulation and is less than or equal to 500 μm, and a second distance exists between a top surface of the strengthening portion and the bottom surface of the encapsulation and is more than or equal to 600 μm. ### Claim 18 (depends on 14) The semiconductor package in accordance with claim 14, wherein a plurality of stiffening ribs are disposed on a recession bottom of the recession.