# US 2022/0037145 A1 · Silicon nitride films having reduced interfacial strain

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- Number: US 2022/0037145 A1
- Document ID: US20220037145A1
- Status: Published application
- Kind: A1
- Application number: 17/377,135
- Filed: 2021-07-15
- Published: 2022-02-03
- Earliest claimed: 2020-07-31
- Assignees: Psiquantum, Corp.
- Applicants: Psiquantum, Corp.
- Inventors: Yong Liang; Ann Melnichuk
- Web page: https://patentgrep.com/patent/US20220037145A1

## CPC

- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In some embodiments a method comprises depositing a first silicon nitride layer on a top surface of a semiconductor wafer and forming one or more first gaps in the first silicon nitride layer. The one or more first gaps can relieve stress formed in the first silicon nitride layer. A first fill material is deposited on the first silicon nitride layer and the first silicon nitride layer is planarized. A second silicon nitride layer is deposited across the first silicon nitride layer and one or more second gaps are formed in the second silicon nitride layer. The one or more second gaps can relieve stress formed in the second silicon nitride layer. A second fill material is deposited across the second silicon nitride layer and the second silicon nitride layer is planarized.

## Claims

### Claim 1

A method comprising:
providing a silicon wafer;
depositing a first portion of a silicon nitride layer on the silicon wafer;
selectively removing first regions of the first portion of the silicon nitride layer along one or more dicing lanes to define one or more first gaps between areas of the first portion of the silicon nitride layer;
depositing a first fill material on the first portion of the silicon nitride layer and into the one or more first gaps;
planarizing a top surface of the first portion of the silicon nitride layer such that the first fill material within the one or more first gaps is coplanar with the top surface of the first portion of the silicon nitride layer;
depositing a second portion of the silicon nitride layer such that it extends across the first portion of the silicon nitride layer and across the first fill material disposed within the one or more first gaps;
selectively removing second regions of the second portion of the silicon nitride layer along the one or more of the dicing lanes to define one or more second gaps between areas of the second portion of the silicon nitride layer;
depositing a second fill material on the second portion of the silicon nitride layer and into the one or more second gaps;
planarizing a top surface of the second portion of the silicon nitride layer such that the second fill material within the one or more second gaps is coplanar with the top surface of the second portion of the silicon nitride layer;
forming one or more additional layers on the top surface of the second portion of the silicon nitride layer; and
forming one or more optical devices on the one or more additional layers.

### Claim 2 (depends on 1)

The method of claim 1 wherein the one or more dicing lanes includes a group of dicing lanes along which one or more first gaps and second gaps are defined.

### Claim 3 (depends on 2)

The method of claim 2 wherein the group includes a repetitive spacing between each of the one or more dicing lanes.

### Claim 4 (depends on 1)

The method of claim 1 wherein the one or more dicing lanes includes a group of dicing lanes having no gaps.

### Claim 5 (depends on 1)

The method of claim 1 wherein the one or more first and second regions are selectively removed using a dicing saw or an etching process.

### Claim 6 (depends on 1)

The method of claim 1 wherein the silicon wafer comprises a silicon-on-insulator series of layers.

### Claim 7

A method comprising:
depositing a first silicon nitride layer on a top surface of a semiconductor wafer;
forming one or more first gaps in the first silicon nitride layer;
depositing a first fill material on the first silicon nitride layer;
planarizing the first silicon nitride layer;
depositing a second silicon nitride layer across the first silicon nitride layer;
forming one or more second gaps in the second silicon nitride layer;
depositing a second fill material across the second silicon nitride layer; and
planarizing the second silicon nitride layer.

### Claim 8 (depends on 7)

The method of claim 7 wherein the semiconductor wafer comprises a silicon wafer.

### Claim 9 (depends on 7)

The method of claim 7 wherein the one or more first and second gaps are formed using a dicing saw or an etching process.

### Claim 10 (depends on 7)

The method of claim 7 wherein the one or more first and second gaps are formed along one or more dicing lanes.

### Claim 11 (depends on 10)

The method of claim 10 wherein the one or more dicing lanes includes a group of dicing lanes along which one or more first and second gaps are formed.

### Claim 12 (depends on 11)

The method of claim 11 wherein the group includes a repetitive spacing between each of the one or more dicing lanes.

### Claim 13 (depends on 10)

The method of claim 10 wherein the one or more dicing lanes includes a group of dicing lanes having no gaps.

### Claim 14 (depends on 7)

The method of claim 7 wherein the one or more first and second gaps are formed within one or more active regions of semiconductor die defined across the semiconductor wafer.

### Claim 15 (depends on 7)

The method of claim 7 wherein the first and second fill materials comprise flowable silicon dioxide.

### Claim 16 (depends on 7)

The method of claim 7 wherein the semiconductor wafer comprises a silicon-on-insulator series of layers.

### Claim 17 (depends on 7)

The method of claim 7 further comprising depositing one or more additional layers on the second silicon nitride layer and forming one or more optical devices on the one or more additional layers.

### Claim 18

A wafer comprising:
a silicon layer;
a silicon nitride layer on the silicon layer wherein the silicon nitride layer defines one or more gaps between regions of the silicon nitride layer; and
silicon dioxide disposed within the one or more gaps and having a top surface coplanar with a top surface of the silicon nitride layer.

### Claim 19 (depends on 18)

The wafer of claim 18 wherein the wafer comprises a silicon-on insulator series of layers.

### Claim 20 (depends on 18)

The wafer of claim 18 further comprising an array of die regions separated by dicing lanes.

### Claim 21 (depends on 20)

The wafer of claim 20 wherein the one or more gaps are defined along one or more of the dicing lanes.

### Claim 22 (depends on 20)

The wafer of claim 20 wherein the one or more gaps are defined within one or more of the die regions.