# US 2022/0036802 A1 · Scan driver and display device

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- Number: US 2022/0036802 A1
- Document ID: US20220036802A1
- Status: Published application
- Kind: A1
- Application number: 17/382,471
- Filed: 2021-07-22
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Sunghwan KIM; Jung Hoon SHIM
- Web page: https://patentgrep.com/patent/US20220036802A1

## CPC

- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/3677: {suitable for active matrices only}
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
- G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A scan driver of a display device includes a plurality of stages. Each stage includes a clock line configured to receive a first clock signal and a second clock signal having different phases, a shared input circuit configured to transfer an input signal to a shared control node, a first output circuit coupled to the shared control node, configured to transfer a voltage of the shared control node to a first control node, and configured to output a first scan signal in response to a voltage of the first control node and the first clock signal, and a second output circuit coupled to the shared control node, configured to transfer the voltage of the shared control node to a second control node, and configured to output a second scan signal in response to a voltage of the second control node and the second clock signal.

## Claims

### Claim 1

A scan driver comprising a plurality of stages, each stage comprising:
at least one clock line configured to receive a first clock signal and a second clock signal having different phases;
a shared input circuit configured to transfer an input signal to a shared control node;
a first output circuit coupled to the shared control node, configured to transfer a voltage of the shared control node to a first control node, and configured to output a first scan signal in response to a voltage of the first control node and the first clock signal; and
a second output circuit coupled to the shared control node, configured to transfer the voltage of the shared control node to a second control node, and configured to output a second scan signal in response to a voltage of the second control node and the second clock signal.

### Claim 2 (depends on 1)

The scan driver of claim 1, wherein the shared input circuit includes:
a first transistor including a gate receiving the input signal, a first terminal receiving the input signal, and a second terminal coupled to the shared control node.

### Claim 3 (depends on 1)

The scan driver of claim 1, wherein the shared input circuit includes:
a first transistor including a gate receiving the second clock signal, a first terminal receiving the input signal, and a second terminal coupled to the shared control node.

### Claim 4 (depends on 1)

The scan driver of claim 1, wherein the first output circuit and the second output circuit are commonly coupled to a shared inverted control node,
wherein the first output circuit transfers a gate-off voltage to a first output node at which the first scan signal is output in response to a voltage of the shared inverted control node, and
wherein the second output circuit transfers the gate-off voltage to a second output node at which the second scan signal is output in response to the voltage of the shared inverted control node.

### Claim 5 (depends on 1)

The scan driver of claim 1, wherein the first output circuit includes:
a second transistor including a gate receiving a gate-on voltage, a first terminal coupled to the shared control node, and a second terminal coupled to the first control node;
a third transistor including a gate coupled to the first control node, a first terminal receiving the first clock signal, and a second terminal coupled to a first output node at which the first scan signal is output;
a first capacitor including a first electrode coupled to the first control node, and a second electrode coupled to the first output node; and
a fourth transistor including a gate coupled to a shared inverted control node, a first terminal coupled to the first output node, and a second terminal receiving a gate-off voltage.

### Claim 6 (depends on 1)

The scan driver of claim 1, wherein the second output circuit includes:
a fifth transistor including a gate receiving the first clock signal, a first terminal coupled to the shared control node, and a second terminal coupled to the second control node;
a sixth transistor including a gate coupled to the second control node, a first terminal receiving the second clock signal, and a second terminal coupled to a second output node at which the second scan signal is output;
a second capacitor including a first electrode coupled to the second control node, and a second electrode coupled to the second output node; and
a seventh transistor including a gate coupled to a shared inverted control node, a first terminal coupled to the second output node, and a second terminal receiving a gate-off voltage.

### Claim 7 (depends on 6)

The scan driver of claim 6, wherein the second output circuit further includes:
a thirteenth transistor coupled between the second terminal of the fifth transistor and the second control node, and including a gate receiving a gate-on voltage, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the second control node.

### Claim 8 (depends on 1)

The scan driver of claim 1, wherein each stage further comprises:
a shared stabilizer circuit configured to transfer a gate-off voltage to the shared control node in response to a voltage of a shared inverted control node.

### Claim 9 (depends on 8)

The scan driver of claim 8, wherein the shared stabilizer circuit includes:
an eighth transistor including a gate coupled to the shared inverted control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate-off voltage.

### Claim 10 (depends on 1)

The scan driver of claim 1, wherein each stage further comprises:
a shared inverter circuit configured to control a shared inverted control node in response to the first clock signal and the first scan signal.

### Claim 11 (depends on 10)

The scan driver of claim 10, wherein the shared inverter circuit includes:
a ninth transistor including a gate receiving the first clock signal, a first terminal receiving the first clock signal, and a second terminal;
a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverted control node;
an eleventh transistor including a gate coupled to a first output node at which the first scan signal is output, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate-off voltage; and
a twelfth transistor including a gate coupled to the first output node, a first terminal coupled to the shared inverted control node, and a second terminal receiving the gate-off voltage.

### Claim 12 (depends on 1)

The scan driver of claim 1, wherein each stage further comprises:
a shared inverter circuit configured to control a shared inverted control node in response to the first clock signal and the voltage of the shared control node.

### Claim 13 (depends on 12)

The scan driver of claim 12, wherein the shared inverter circuit includes:
a ninth transistor including a gate receiving the first clock signal, a first terminal receiving the first clock signal, and a second terminal;
a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverted control node;
an eleventh transistor including a gate coupled to the shared control node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving a gate-off voltage;
a twelfth transistor including a gate coupled to the shared control node, a first terminal coupled to the shared inverted control node, and a second terminal receiving the gate-off voltage; and
a third capacitor including a first electrode coupled to the shared inverted control node, and a second electrode receiving the gate-off voltage.

### Claim 14 (depends on 1)

The scan driver of claim 1, wherein transistors included in at least one of the first output circuit or the second output circuit of the scan driver are NMOS transistors, and transistors included in at least the other of the first output circuit or the second output circuit are PMOS transistors.

### Claim 15 (depends on 1)

The scan driver of claim 1, wherein transistors included in at least one of the shared input circuit, the shared stabilizer circuit or the shared inverter circuit of the scan driver are PMOS transistors, and transistors included in at least another of the shared input circuit, the shared stabilizer circuit or the shared inverter circuit are NMOS transistors.

### Claim 16

A scan driver comprising a plurality of stages, each stage comprising:
at least one clock line configured to receive a first clock signal and a second clock signal having different phases;
a first transistor including a gate receiving an input signal or the second clock signal, a first terminal receiving the input signal, and a second terminal coupled to a shared control node;
a second transistor including a gate receiving a gate-on voltage, a first terminal coupled to the shared control node, and a second terminal coupled to a first control node;
a third transistor including a gate coupled to the first control node, a first terminal receiving the first clock signal, and a second terminal coupled to a first output node at which a first scan signal is output;
a first capacitor including a first electrode coupled to the first control node, and a second electrode coupled to the first output node;
a fourth transistor including a gate coupled to a shared inverted control node, a first terminal coupled to the first output node, and a second terminal receiving a gate-off voltage;
a fifth transistor including a gate receiving the first clock signal, a first terminal coupled to the shared control node, and a second terminal coupled to a second control node;
a sixth transistor including a gate coupled to the second control node, a first terminal receiving the second clock signal, and a second terminal coupled to a second output node at which a second scan signal is output;
a second capacitor including a first electrode coupled to the second control node, and a second electrode coupled to the second output node; and
a seventh transistor including a gate coupled to the shared inverted control node, a first terminal coupled to the second output node, and a second terminal receiving the gate-off voltage.

### Claim 17 (depends on 16)

The scan driver of claim 16, wherein each stage further comprises:
an eighth transistor including a gate coupled to the shared inverted control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate-off voltage;
a ninth transistor including a gate receiving the first clock signal, a first terminal receiving the first clock signal, and a second terminal;
a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverted control node;
an eleventh transistor including a gate coupled to the first output node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving the gate-off voltage; and
a twelfth transistor including a gate coupled to the first output node, a first terminal coupled to the shared inverted control node, and a second terminal receiving the gate-off voltage.

### Claim 18 (depends on 16)

The scan driver of claim 16, wherein each stage further comprises:
a thirteenth transistor coupled between the second terminal of the fifth transistor and the second control node, and including a gate receiving the gate-on voltage, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the second control node.

### Claim 19 (depends on 16)

The scan driver of claim 16, wherein each stage further comprises:
an eighth transistor including a gate coupled to the shared inverted control node, a first terminal coupled to the shared control node, and a second terminal receiving the gate-off voltage;
a ninth transistor including a gate receiving the first clock signal, a first terminal receiving the first clock signal, and a second terminal;
a tenth transistor including a gate coupled to the second terminal of the ninth transistor, a first terminal receiving the first clock signal, and a second terminal coupled to the shared inverted control node;
an eleventh transistor including a gate coupled to the shared control node, a first terminal coupled to the gate of the tenth transistor, and a second terminal receiving the gate-off voltage;
a twelfth transistor including a gate coupled to the shared control node, a first terminal coupled to the shared inverted control node, and a second terminal receiving the gate-off voltage; and
a third capacitor including a first electrode coupled to the shared inverted control node, and a second electrode receiving the gate-off voltage.

### Claim 20

A display device comprising:
a display panel including a plurality of pixels;
a data driver configured to provide data signals to the plurality of pixels;
a scan driver configured to provide scan signals to the plurality of pixels, and including a plurality of stages; and
a controller configured to control the data driver and the scan driver,
wherein each of the plurality of stages includes:
at least one clock line configured to receive a first clock signal and a second clock signal having different phases;
a shared input circuit configured to transfer an input signal to a shared control node;
a first output circuit coupled to the shared control node, configured to transfer a voltage of the shared control node to a first control node, and configured to output a first scan signal of the scan signals in response to a voltage of the first control node and the first clock signal; and
a second output circuit coupled to the shared control node, configured to transfer the voltage of the shared control node to a second control node, and configured to output a second scan signal of the scan signals in response to a voltage of the second control node and the second clock signal.