# US 2022/0036788 A1 · Shift register and method for driving the same, gate driving circuit, and display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0036788 A1 - Document ID: US20220036788A1 - Status: Published application - Kind: A1 - Application number: 17/278,507 - Filed: 2020-05-09 - Published: 2022-02-03 - Earliest claimed: 2019-05-13 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Lubin SHI; Xiaohai CHEN - Web page: https://patentgrep.com/patent/US20220036788A1 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A shift register includes an output sub-circuit and a coupling sub-circuit. The output sub-circuit is coupled to a second clock signal terminal, a pull-up node and a signal output terminal. The output sub-circuit is configured to output a second clock signal received at the second clock signal terminal to the signal output terminal under a control of a voltage of the pull-up node. The coupling sub-circuit is coupled to the second clock signal terminal and a pull-down node. The coupling sub-circuit is configured to couple a voltage of the pull-down node through the second clock signal received at the second clock signal terminal. ## Claims ### Claim 1 A shift register, comprising an output sub-circuit and a coupling sub-circuit, wherein the output sub-circuit is coupled to a second clock signal terminal, a pull-up node and a signal output terminal, and the output sub-circuit is configured to output a second clock signal received at the second clock signal terminal to the signal output terminal under a control of a voltage of the pull-up node; and the coupling sub-circuit is coupled to the second clock signal terminal and a pull-down node, and the coupling sub-circuit is configured to couple a voltage of the pull-down node through the second clock signal received at the second clock signal terminal. ### Claim 2 (depends on 1) The shift register according to claim 1, wherein the output sub-circuit includes a first transistor and a first capacitor; a control electrode of the first transistor is coupled to the pull-up node, a first electrode of the first transistor is coupled to the second clock signal terminal, and a second electrode of the first transistor is coupled to the signal output terminal; a first electrode of the first capacitor is coupled to the pull-up node, and a second electrode of the first capacitor is coupled to the signal output terminal; and the coupling sub-circuit includes a second capacitor; a first electrode of the second capacitor is coupled to the pull-down node, and a second electrode of the second capacitor is coupled to the second clock signal terminal. ### Claim 3 (depends on 1) The shift register according to claim 1, further comprising a first control sub-circuit; the first control sub-circuit being coupled to the signal output terminal, a first voltage signal terminal and the pull-down node, and the first control sub-circuit being configured to output a first voltage signal received at the first voltage signal terminal to the pull-down node under a control of a voltage of the signal output terminal. ### Claim 4 (depends on 3) The shift register according to claim 3, wherein the first control sub-circuit includes a second transistor; a control electrode of the second transistor is coupled to the signal output terminal, a first electrode of the second transistor is coupled to the first voltage signal terminal, and a second electrode of the second transistor is coupled to the pull-down node. ### Claim 5 (depends on 1) The shift register according to claim 1, further comprising a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit and an energy storage sub-circuit, wherein the second control sub-circuit is coupled to the pull-up node, a first voltage signal terminal and the pull-down node, and the second control sub-circuit is configured to output a first voltage signal received at the first voltage signal terminal to the pull-down node under the control of the voltage of the pull-up node; the third control sub-circuit is coupled to the pull-up node, the pull-down node and the first voltage signal terminal, and the third control sub-circuit is configured to output the first voltage signal received at the first voltage signal terminal to the pull-up node under the control of the voltage of the pull-down node; the fourth control sub-circuit is coupled to a third clock signal terminal, a second voltage signal terminal and the pull-down node, and the fourth control sub-circuit is configured to output a second voltage signal received at the second voltage signal terminal to the pull-down node in response to a third clock signal received at the third voltage signal terminal; and the energy storage sub-circuit is coupled to the pull-down node and the first voltage signal terminal, and the energy storage sub-circuit is configured to perform charging and discharging under the control of the voltage of the pull-down node. ### Claim 6 (depends on 5) The shift register according to claim 5, wherein the second control sub-circuit includes a third transistor; a control electrode of the third transistor is coupled to the pull-up node, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the pull-down node; the third control sub-circuit includes a fifth transistor; a control electrode of the fifth transistor is coupled to the pull-down node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the pull-up node; the fourth control sub-circuit includes a sixth transistor; a control electrode of the sixth transistor is coupled to the third clock signal terminal, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the pull-down node; and the energy storage sub-circuit includes a third capacitor; a first electrode of the third capacitor is coupled to the pull-down node, and a second electrode of the third capacitor is coupled to the first voltage signal terminal. ### Claim 7 (depends on 5) The shift register according to claim 5, further comprising a fifth control sub-circuit; the fifth control sub-circuit being coupled to a signal input terminal, the first voltage signal terminal and the pull-down node; the fifth control sub-circuit being configured to output the first voltage signal received at the first voltage signal terminal to the pull-down node in response to a turn-on signal received at the signal input terminal. ### Claim 8 (depends on 7) The shift register according to claim 7, wherein the fifth control sub-circuit includes a seventh transistor; a control electrode of the seventh transistor is coupled to the signal input terminal, a first electrode of the seventh transistor is coupled to the first voltage signal terminal, and a second electrode of the seventh transistor is coupled to the pull-down node. ### Claim 9 (depends on 1) The shift register according to claim 1, further comprising an input sub-circuit and a pull-down sub-circuit, wherein the input sub-circuit is coupled to a signal input terminal, a second voltage signal terminal and the pull-up node, and the input sub-circuit is configured to output a second voltage signal received at the second voltage signal terminal to the pull-up node in response to a turn-on signal received at the signal input terminal; the pull-down sub-circuit is coupled to the pull-down node, a first voltage signal terminal and the signal output terminal, and the pull-down sub-circuit is configured to output a first voltage signal received at the first voltage signal terminal to the signal output terminal under the control of the voltage of the pull-down node. ### Claim 10 (depends on 9) The shift register according to claim 9, wherein the input sub-circuit includes an eighth transistor; a control electrode of the eighth transistor is coupled to the signal input terminal, a first electrode of the eighth transistor is coupled to the second voltage signal terminal, and a second electrode of the eighth transistor is coupled to the pull-up node; the pull-down sub-circuit includes a tenth transistor; a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the signal output terminal. ### Claim 11 (depends on 1) The shift register according to claim 1, further comprising a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, an energy storage sub-circuit, a fifth control sub-circuit, an input sub-circuit and a pull-down sub-circuit, wherein the output sub-circuit includes a first transistor and a first capacitor; the coupling sub-circuit includes a second capacitor; the first control sub-circuit includes a second transistor; the second control sub-circuit includes a third transistor and a fourth transistor; the third control sub-circuit includes a fifth transistor; the fourth control sub-circuit includes a sixth transistor; the energy storage sub-circuit includes a third capacitor; the fifth control sub-circuit includes a seventh transistor; the input sub-circuit includes an eighth transistor and a ninth transistor; the pull-down sub-circuit includes a tenth transistor; a control electrode of the first transistor is coupled to the pull-up node, a first electrode of the first transistor is coupled to the second clock signal terminal, and a second electrode of the first transistor is coupled to the signal output terminal; a first electrode of the first capacitor is coupled to the pull-up node, and a second electrode of the first capacitor is coupled to the signal output terminal; a first electrode of the second capacitor is coupled to the pull-down node, and a second electrode of the second capacitor is coupled to the second clock signal terminal; a control electrode of the second transistor is coupled to the signal output terminal, a first electrode of the second transistor is coupled to a first voltage signal terminal, and a second electrode of the second transistor is coupled to the pull-down node; a control electrode of the fourth transistor is coupled to a second voltage signal terminal, a first electrode of the fourth transistor is coupled to the pull-up node, and a second electrode of the fourth transistor is coupled to a control electrode of the third transistor; a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the pull-down node; a control electrode of the fifth transistor is coupled to the pull-down node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the pull-up node; a control electrode of the sixth transistor is coupled to a third clock signal terminal, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the pull-down node; a first electrode of the third capacitor is coupled to the pull-down node, and a second electrode of the third capacitor is coupled to the first voltage signal terminal; a control electrode of the seventh transistor is coupled to a signal input terminal, a first electrode of the seventh transistor is coupled to the first voltage signal terminal, and a second electrode of the seventh transistor is coupled to the pull-down node; a control electrode of the eighth transistor is coupled to the signal input terminal, a first electrode of the eighth transistor is coupled to the second voltage signal terminal, and a second electrode of the eighth transistor is coupled to a first electrode of the ninth transistor; a control electrode of the ninth transistor is coupled to a first clock signal terminal, and a second electrode of the ninth transistor is coupled to the pull-up node; and a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the signal output terminal. ### Claim 12 (depends on 1) A gate driving circuit, comprising N stages of cascaded shift registers according to claim 1. ### Claim 13 (depends on 12) A display apparatus, comprising the gate driving circuit according to claim 12. ### Claim 14 (depends on 1) A method for driving the shift register according to claim 1, comprising: in an output phase, the output sub-circuit being turned on under the control of the voltage of the pull-up node to output the second clock signal received at the second clock signal terminal as a scanning signal to the signal output terminal; and after the output phase, in a phase in which a voltage of the second clock signal is same as a voltage of the second clock signal in the output phase, the coupling sub-circuit coupling the voltage of the pull-down node through the second clock signal. ### Claim 15 (depends on 1) The shift register according to claim 1, further comprising a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit and an energy storage sub-circuit, wherein the second control sub-circuit is coupled to the pull-up node, a first voltage signal terminal, a second voltage signal terminal and the pull-down node, and the second control sub-circuit is configured to output a first voltage signal received at the first voltage signal terminal to the pull-down node in response to the voltage of the pull-up node and a second voltage signal received at the second voltage signal terminal; the third control sub-circuit is coupled to the pull-up node, the pull-down node and the first voltage signal terminal, and the third control sub-circuit is configured to output the first voltage signal received at the first voltage signal terminal to the pull-up node under the control of the voltage of the pull-down node; the fourth control sub-circuit is coupled to a third clock signal terminal, the second voltage signal terminal and the pull-down node, and the fourth control sub-circuit is configured to output the second voltage signal received at the second voltage signal terminal to the pull-down node in response to a third clock signal received at the third voltage signal terminal; and the energy storage sub-circuit is coupled to the pull-down node and the first voltage signal terminal, and the energy storage sub-circuit is configured to perform charging and discharging under the control of the voltage of the pull-down node. ### Claim 16 (depends on 15) The shift register according to claim 15, wherein the second control sub-circuit includes a third transistor and a fourth transistor; a control electrode of the fourth transistor is coupled to the second voltage signal terminal, a first electrode of the fourth transistor is coupled to the pull-up node, a second electrode of the fourth transistor is coupled to a control electrode of the third transistor, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the pull-down node; the third control sub-circuit includes a fifth transistor; a control electrode of the fifth transistor is coupled to the pull-down node, a first electrode of the fifth transistor is coupled to the first voltage signal terminal, and a second electrode of the fifth transistor is coupled to the pull-up node; the fourth control sub-circuit includes a sixth transistor; a control electrode of the sixth transistor is coupled to the third clock signal terminal, a first electrode of the sixth transistor is coupled to the second voltage signal terminal, and a second electrode of the sixth transistor is coupled to the pull-down node; and the energy storage sub-circuit includes a third capacitor; a first electrode of the third capacitor is coupled to the pull-down node, and a second electrode of the third capacitor is coupled to the first voltage signal terminal. ### Claim 17 (depends on 15) The shift register according to claim 15, further comprising a fifth control sub-circuit; the fifth control sub-circuit being coupled to a signal input terminal, the first voltage signal terminal and the pull-down node; the fifth control sub-circuit being configured to output the first voltage signal received at the first voltage signal terminal to the pull-down node in response to a turn-on signal received at the signal input terminal. ### Claim 18 (depends on 1) The shift register according to claim 1, further comprising an input sub-circuit and a pull-down sub-circuit, wherein the input sub-circuit is coupled to a signal input terminal, a second voltage signal terminal, a first clock signal terminal and the pull-up node, and the input sub-circuit is configured to output a second voltage signal received at the second voltage signal terminal to the pull-up node in response to a turn-on signal received at the signal input terminal and a first clock signal received at the first clock signal terminal; and the pull-down sub-circuit is coupled to the pull-down node, a first voltage signal terminal and the signal output terminal, and the pull-down sub-circuit is configured to output a first voltage signal received at the first voltage signal terminal to the signal output terminal under the control of the voltage of the pull-down node. ### Claim 19 (depends on 18) The shift register according to claim 18, wherein the input sub-circuit includes an eighth transistor and a ninth transistor; a control electrode of the eighth transistor is coupled to the signal input terminal, a first electrode of the eighth transistor is coupled to the second voltage signal terminal, a second electrode of the eighth transistor is coupled to a first electrode of the ninth transistor, a control electrode of the ninth transistor is coupled to the first clock signal terminal, and a second electrode of the ninth transistor is coupled to the pull-up node; and the pull-down sub-circuit includes a tenth transistor; a control electrode of the tenth transistor is coupled to the pull-down node, a first electrode of the tenth transistor is coupled to the first voltage signal terminal, and a second electrode of the tenth transistor is coupled to the signal output terminal.