# US 2022/0036786 A1 · Timing control board, drive device and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0036786 A1 - Document ID: US20220036786A1 - Status: Published application - Kind: A1 - Application number: 17/201,541 - Filed: 2021-03-15 - Published: 2022-02-03 - Earliest claimed: 2020-07-28 - Assignees: Chongqing Hkc Optoelectronics Technology Co., Ltd.; Hkc Corporation Limited - Applicants: Chongqing Hkc Optoelectronics Technology Co., Ltd.; Hkc Corporation Limited - Inventors: FEILIN JI; LIDAN YE - Web page: https://patentgrep.com/patent/US20220036786A1 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/2088: {with use of a plurality of processors, each processor controlling a number of individual elements of the matrix} - G09G 5/12: Synchronisation between the display unit and other units, e.g. other display units, video-disc players - G09G 2300/0404: Matrix technologies - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0275: Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2370/00: Aspects of data communication - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G 2370/22: Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A timing control board includes a point-to-point interface, a storage, a signal input port and a timing controller. The storage is for storing multiple sets of different point-to-point configuration parameters. The timing controller obtains a set of point-to-point configuration parameters matching a protocol type of a source drive circuit board in the storage according to the configuration parameter selection signal, and initializes settings according to the set of point-to-point configuration parameters to generate matched data signals and output the data signals to the source drive circuit board through the point-to-point interface, so as to realize the compatibility of display panels and reduce the design cost. ## Claims ### Claim 1 A timing control board, comprising: a point-to-point interface for connecting a source drive circuit board and performing point-to-point signal transmission; a storage for storing a plurality of different sets of point-to-point configuration parameters; a signal input interface for receiving a configuration parameter selection signal; and a timing controller connected with the point-to-point interface, the signal input port and the storage, wherein the timing controller is for: obtaining a set of point-to-point configuration parameters in the storage that matches a protocol type of the source drive circuit board according to the configuration parameter selection signal, initializing settings according to the set of point-to-point configuration parameters, to generate matched data signals and clock signals, and outputting the data signals and clock signals to the source driving circuit board through the point-to-point interface. ### Claim 2 (depends on 1) The timing control board of claim 1, wherein the storage is provided with a plurality of storage areas, each of the plurality of storage areas is for storing a set of point-to-point configuration parameters different from sets of point-to-point configuration parameters stored in others of the plurality of storage areas. ### Claim 3 (depends on 1) The timing control board of claim 1, wherein the signal input port comprises a first common port for receiving the configuration parameter selection signal, and a synchronization signal input port for receiving a synchronization drive signal for driving a display panel. ### Claim 4 (depends on 3) The timing control board of claim 3, wherein, the point-to-point interface comprises a first signal interface and a second signal interface, the timing controller is for outputting the clock signals and the data signals through the first signal interface, and outputting a level synchronization signal through the second signal interface, the level synchronization signal is for identifying a level state for clock synchronization between the timing controller and the source drive circuit board in conjunction with the first signal interface. ### Claim 5 (depends on 1) The timing control board of claim 1, wherein the storage is a flash memory or a read-only memory. ### Claim 6 (depends on 1) The timing control board of claim 1, further comprising a connector for connecting the point-to-point interface and the source drive circuit board. ### Claim 7 (depends on 6) The timing control board of claim 6, wherein the connector is a flexible circuit board connector. ### Claim 8 (depends on 1) The timing control board of claim 1, wherein, the timing controller is connected with the storage through a serial peripheral interface, and the timing controller is for outputting a chip selection signal to the storage through the serial peripheral interface to obtain the set of point-to-point configuration parameters in the storage that matches the protocol type of the source drive circuit board, after receiving the configuration parameter selection signal. ### Claim 9 A timing control board, comprising: a point-to-point interface for connecting a source drive circuit board and performing point-to-point signal transmission; a storage provided with a plurality of storage areas, each of the plurality of storage areas being for storing a set of point-to-point configuration parameters different from sets of point-to-point configuration parameters stored in others of the plurality of storage areas; a signal input interface for receiving a configuration parameter selection signal; and a timing controller connected with the point-to-point interface, the signal input port and the storage; wherein the timing controller is connected with the storage through a serial peripheral interface, and the timing controller is for: outputting a chip selection signal to the storage through the serial peripheral interface, to obtain a set of point-to-point configuration parameters in the storage that matches the protocol type of the source drive circuit board, according to the configuration parameter selection signal, initializing settings according to the set of point-to-point configuration parameters, to generate matched data signals and clock signals, and outputting the data signals and clock signals to the source driving circuit board through the point-to-point interface. ### Claim 10 (depends on 1) A drive device, comprising: a source drive circuit board connected with a data line a scanning line of a display panel and for outputting analog gray scale voltage signals to drive the display panel; a gate drive circuit board connected with a scanning line of the display panel and for outputting row scanning signals to drive the display panel; and a timing control board of claim 1 connected with the source drive circuit board and the gate drive circuit board. ### Claim 11 (depends on 10) The drive device of claim 10, wherein the storage is provided with a plurality of storage areas, each of the plurality of storage areas is for storing a set of point-to-point configuration parameters different from sets of point-to-point configuration parameters stored in others of the plurality of storage areas. ### Claim 12 (depends on 10) The drive device of claim 10, wherein the signal input port comprises a first common port for receiving the configuration parameter selection signal, and a synchronization signal input port for receiving a synchronization drive signal for driving a display panel. ### Claim 13 (depends on 12) The drive device of claim 12, wherein, the point-to-point interface comprises a first signal interface and a second signal interface, the timing controller is for outputting the clock signals and the data signals through the first signal interface, and outputting a level synchronization signal through the second signal interface, the level synchronization signal is for identifying a level state for clock synchronization between the timing controller and the source drive circuit board in conjunction with the first signal interface. ### Claim 14 (depends on 10) The drive device of claim 10, wherein the storage is a flash memory or a read-only memory. ### Claim 15 (depends on 10) The drive device of claim 10, further comprising a connector for connecting the point-to-point interface and the source drive circuit board. ### Claim 16 (depends on 15) The drive device of claim 15, wherein the connector is a flexible circuit board connector. ### Claim 17 (depends on 10) The drive device of claim 10, wherein, the timing controller is connected with the storage through a serial peripheral interface, and the timing controller is for outputting a chip selection signal to the storage through the serial peripheral interface, to obtain the set of point-to-point configuration parameters in the storage that matches the protocol type of the source drive circuit board, after receiving the configuration parameter selection signal. ### Claim 18 (depends on 9) A display device comprising a display panel and a drive device of claim 9, wherein a signal terminal of the display panel is connected to a signal terminal of the drive device.