# US 2022/0036780 A1 · Electrical conductivity test structure, thin film transistor array substrate, and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0036780 A1 - Document ID: US20220036780A1 - Status: Published application - Kind: A1 - Application number: 17/206,747 - Filed: 2021-03-19 - Published: 2022-02-03 - Earliest claimed: 2020-07-31 - Assignees: Century Technology (Shenzhen) Corporation Limited - Applicants: Century Technology (Shenzhen) Corporation Limited - Inventors: QI XU; RUI LI; YUAN XIONG; HUI WANG; WEN-LIN CHEN; CHIH-CHUNG LIU - Web page: https://patentgrep.com/patent/US20220036780A1 ## CPC - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G01N 27/04: by investigating resistance - G02F 1/1309: {Repairing; Testing} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract An electrical conductivity test structure for testing an electrical conductivity of target traces in a display panel includes a controller, a first conductive layer, and a second conductive layer. The first conductive layer includes first and second traces. The at least one first trace and the at least one second trace are connected in parallel. Each first trace connects with the target trace and with the controller and each second trace connects with the target trace and with the controller. The second conductive layer connects with the first trace but is electrically insulated from the second trace. The second conductive layer transmits test signals to the first trace to test electrical conductivity between the controller and the target trace. ## Claims ### Claim 1 An electrical conductivity test structure configured for testing an electrical conductivity of a target trace in a display panel comprising a controller, the electrical conductivity test structure comprising: a first conductive layer comprising at least one first trace and at least one second trace, the at least one first trace and the at least one second trace being connected in parallel, each of the at least one first trace being electrically connected to the target trace and the controller, and each of the at least one second trace being electrically connected with the target trace and the controller; and a second conductive layer electrically connected with the at least one first trace and electrically insulated from the at least one second trace, the second conductive layer being configured to transmit test signals to the at least one first trace; wherein the test signals are configured to test an electrical conductivity between the controller and the target trace. ### Claim 2 (depends on 1) The electrical conductivity test structure of claim 1, further comprising: a first insulating layer between the first conductive layer and the second conductor layer, the first insulating layer electrically insulating the at least one second trace and the second conductive layer, wherein the first insulating layer defines a plurality of first through holes, and the second conductive layer is electrically connected with the at least one first trace by the second conductive layer extending to the plurality of first through holes. ### Claim 3 (depends on 2) The electrical conductivity test structure of claim 2, further comprising: a third conductive layer between the second conductive layer and the first conductive layer and electrically connected with the first conductive layer through the second conductive layer. ### Claim 4 (depends on 3) The electrical conductivity test structure of claim 3, further comprising: a second insulating layer between the first conductive layer and the third conductive layer, the second insulating layer being configured for electrically insulating the at least one second trace and the third conductive layer, wherein the second insulating layer defines a plurality of second through holes, and the second conductive layer is electrically connected with the third conductive layer by the second conductive layer extending to the plurality of second through holes. ### Claim 5 (depends on 1) The electrical conductivity test structure of claim 1, wherein the first conductive layer is made of metal, and the second conductive layer is made of indium tin oxide. ### Claim 6 A thin film transistor array substrate, comprising: a glass substrate defining a display area and a non-display area connected with the display area, the target trace being in the display area, and the controller being in the non-display area; and an electrical conductivity test structure, comprising: a first conductive layer comprising at least one first trace and at least one second trace, the at least one first trace and the at least one second trace are connected in parallel, each of the at least one first trace electrically connected to the target trace and the controller, and each of the at least one second trace electrically connected with the target trace and the controller; and a second conductive layer electrically connected with the at least one first trace and electrically insulated from the at least one second trace, the second conductive layer configured to transmit test signals to the at least one first trace; wherein the test signals are configured to test an electrical conductivity between the controller and the target trace. ### Claim 7 (depends on 6) The thin film transistor array substrate of claim 6, wherein the electrical conductivity test structure further comprises: a first insulating layer between the first conductive layer and the second conductor layer for electrically insulating the at least one second trace and the second conductive layer; wherein the first insulating layer defines a plurality of first through holes, and the second conductive layer is electrically connected with the at least one first trace by the second conductive layer extending to the plurality of first through holes. ### Claim 8 (depends on 7) The thin film transistor array substrate of claim 7, wherein the electrical conductivity test structure further comprises: a third conductive layer between the second conductive layer and the first conductive layer and electrically connected with the first conductive layer through the second conductive layer. ### Claim 9 (depends on 8) The thin film transistor array substrate of claim 8, wherein the electrical conductivity test structure further comprises: a second insulating layer between the first conductive layer and the third conductive layer for electrically insulating the at least one second trace and the third conductive layer; wherein the second insulating layer defines a plurality of second through holes, and the second conductive layer is electrically connected with the third conductive layer by the second conductive layer extending to the plurality of second through holes. ### Claim 10 (depends on 6) The thin film transistor array substrate of claim 6, wherein the first conductive layer is made of metal, and the second conductive layer is made of indium tin oxide. ### Claim 11 (depends on 6) The thin film transistor array substrate of claim 6, wherein the electrical conductivity test structure is in the non-display area. ### Claim 12 (depends on 7) The thin film transistor array substrate of claim 7, wherein the electrical conductivity test structure is in the non-display area. ### Claim 13 (depends on 6) The thin film transistor array substrate of claim 6, wherein the target trace is a gate line; or the target trace is a data line; or the target trace comprises the gate line and the data line. ### Claim 14 (depends on 7) The thin film transistor array substrate of claim 7, wherein the target trace is a gate line; or the target trace is a data line; or the target trace comprises the gate line and the data line. ### Claim 15 A display panel, comprising: a color filter substrate; a thin film transistor array substrate comprising: a glass substrate defined a display area and a non-display area connected with the display area, the target trace being in the display area, and the controller being in the non-display area; and an electrical conductivity test structure, comprising: a first conductive layer comprising at least one first trace and at least one second trace, the at least one first trace and the at least one second trace are connected in parallel, each of the at least one first trace electrically connected to the target trace and the controller, and each of the at least one second trace electrically connected with the target trace and the controller; and a second conductive layer electrically connected with the at least one first trace and electrically insulated from the at least one second trace, the second conductive layer configured to transmit test signals to the at least one first trace; wherein the test signals are configured to test an electrical conductivity between the controller and the target trace; and a liquid crystal layer between the color filter substrate and the thin film transistor array substrate, the color filter substrate, the liquid crystal layer, and the thin film transistor array substrate configured to display images in cooperation. ### Claim 16 (depends on 13) The display panel of claim 13, wherein the electrical conductivity test structure is in the non-display area. ### Claim 17 (depends on 13) The display panel of claim 13, wherein the target trace is a gate line; or the target trace is a data line; or the target trace comprises the gate line and the data line. ### Claim 18 (depends on 13) The display panel of claim 13, wherein the controller is configured to output a display signal to the target trace through the at least one first trace when the display panel displays images; or the controller is configured to output a display signal to the target trace through the at least one second trace when the display panel displays images; or the controller is configured to output a display signal to the target trace through the at least one first trace and the at least one second trace when the display panel displays images.