# US 2022/0036639 A1 · Ray Intersect Circuitry with Parallel Ray Testing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0036639 A1 - Document ID: US20220036639A1 - Status: Published application - Kind: A1 - Application number: 17/103,433 - Filed: 2020-11-24 - Published: 2022-02-03 - Earliest claimed: 2020-07-30 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Ali Rabbani Rankouhi; Christopher A. Burns; Justin A. Hensley; Luca Iuliano; Jonathan M. Redshaw - Web page: https://patentgrep.com/patent/US20220036639A1 ## CPC - G06T 15/06: Ray-tracing - G06T 15/005: {General purpose rendering architectures} - G06T 17/005: {Tree description, e.g. octree, quadtree} - G06T 2210/12: Bounding box - G06T 2210/21: Collision detection, intersection - G06T 2210/52: Parallel processing - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques. ## Claims ### Claim 1 An apparatus, comprising: graphics shader circuitry configured to executing a ray intersect instruction that indicates origin and direction information for a set of one or more rays in a graphics scene; ray intersect circuitry configured to: traverse, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure, wherein nodes of the data structure indicate coordinates corresponding to bounding regions in the graphics scene; test in parallel, using bounding region test circuitry during the traversal, whether a ray in the set of rays intersects multiple different bounding regions indicated by a node of the data structure; and wherein the apparatus is configured to determine, based on the traversal and tests, information specifying one or more graphics primitives intersected by respective rays in the set of one or more rays; and wherein the graphics shader circuitry is configured to shade the specified one or more graphics primitives based on intersecting rays. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the bounding region test circuitry is configured to test multiple rays in parallel against the multiple different bounding regions. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the bounding region test circuitry includes: multiple bounding region testers configured to determine whether a ray intersects a bounding region and configured to perform the testing for multiple bounding regions in parallel; and common node calculation circuitry configured to perform one or more operations whose outputs are shared by the bounding region testers. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the bounding region test circuitry further includes: a bounding region data cache; a ray data cache; and result ordering circuitry configured to order intersection results from the multiple bounding region testers based on distance to an origin of a ray being tested. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the apparatus is configured to store ray data for the set of one or more rays in a shader memory space that is accessible to the graphics shader circuitry and the ray intersect circuitry. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the graphics shader circuitry is configured to generate one or more additional rays based on shading of the specified one or more graphics primitives and execute a ray intersect instruction for the one or more additional rays. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the acceleration data structure is a hierarchical structure and a first node is a leaf node of an upper level acceleration data structure that has a child node in a lower level acceleration data structure; wherein the lower level acceleration data structure corresponds to a graphics model that is instantiated in the graphics scene multiple times; and wherein the ray intersect circuitry is configured to form a SIMD group to transform coordinates of one or more rays that reach the first node to a model space of an instance of the graphics model. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein one or more nodes of the acceleration data structure include four or more bounding regions and four or more child nodes. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the acceleration data structure includes a node with a bounding region for which multiple primitives are indicated as children; and wherein the acceleration data structure includes a primitive for which multiple bounding regions are indicated as parents. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the ray intersect circuitry is configured to form a SIMD group to test a set of rays against a primitive corresponding to a leaf node of the data structure. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the ray intersect circuitry is configured to group, using grouping circuitry, portions of the set of rays into multiple groups based on the node of the data structure that they target next, wherein the testing is based on the groups. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the apparatus is a computing device that includes: a graphics processor that includes the ray intersect circuitry; a central processing unit; and network interface circuitry. ### Claim 13 A method, comprising: executing, by graphics shader circuitry, a ray intersect instruction that indicates origin and direction information for a set of one or more rays in a graphics scene; traversing, by ray intersect circuitry in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure, wherein nodes of the data structure indicate coordinates corresponding to bounding regions in the graphics scene; testing, by the ray intersect circuitry in parallel, whether a ray in the set of rays intersects multiple different bounding regions indicated by a node of the data structure, using bounding region test circuitry during the traversal, determining, based on the traversing and testing, information specifying one or more graphics primitives intersected by respective rays in the set of one or more rays; and shading, by the graphics shader circuitry, shade the specified one or more graphics primitives based on intersecting rays. ### Claim 14 (depends on 13) The method of claim 13, further comprising: generating, one or more additional rays based on shading of the specified one or more graphics primitives; and executing a ray intersect instruction for the one or more additional rays. ### Claim 15 (depends on 13) The method of claim 13, further comprising: test multiple rays in parallel against the multiple different bounding regions. ### Claim 16 A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit includes: graphics shader circuitry configured to executing a ray intersect instruction that indicates origin and direction information for a set of one or more rays in a graphics scene; ray intersect circuitry configured to: traverse, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure, wherein nodes of the data structure indicate coordinates corresponding to bounding regions in the graphics scene; test in parallel, using bounding region test circuitry during the traversal, whether a ray in the set of rays intersects multiple different bounding regions indicated by a node of the data structure; and wherein the circuit is configured to determine, based on the traversal and tests, information specifying one or more graphics primitives intersected by respective rays in the set of one or more rays; and wherein the graphics shader circuitry is configured to shade the specified one or more graphics primitives based on intersecting rays. ### Claim 17 (depends on 16) The non-transitory computer readable storage medium of claim 16, wherein the bounding region test circuitry is configured to test multiple rays in parallel against the multiple different bounding regions. ### Claim 18 (depends on 16) The non-transitory computer readable storage medium of claim 16, wherein the bounding region test circuitry includes: multiple bounding region testers configured to determine whether a ray intersects a bounding region and configured to perform the testing for multiple bounding regions in parallel; and common node calculation circuitry configured to perform one or more operations whose outputs are shared by the bounding region testers. ### Claim 19 (depends on 18) The non-transitory computer readable storage medium of claim 18, wherein the bounding region test circuitry further includes: a bounding region data cache; a ray data cache; and result ordering circuitry configured to order intersection results from the multiple bounding region testers based on distance to an origin of a ray being tested. ### Claim 20 (depends on 16) The non-transitory computer readable storage medium of claim 16, wherein the graphics shader circuitry is configured to generate one or more additional rays based on shading of the specified one or more graphics primitives and execute a ray intersect instruction for the one or more additional rays.