# US 2022/0036632 A1 · Post-processing in a memory-system efficient manner

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- Number: US 2022/0036632 A1
- Document ID: US20220036632A1
- Status: Published application
- Kind: A1
- Application number: 17/187,729
- Filed: 2021-02-26
- Published: 2022-02-03
- Earliest claimed: 2020-08-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Raun M. KRISCH; David C. TANNENBAUM; Moumine BALLO; Keshavan VARADARAJAN
- Web page: https://patentgrep.com/patent/US20220036632A1

## CPC

- G06T 15/005: {General purpose rendering architectures}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06T 1/60: Memory management
- G06T 15/80: Shading
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A GPU includes one or more post-processing controllers, and a 3D graphics pipeline including a post-processing shader stage following a pixel shader stage. The one or more post-processing controllers may synchronize an execution of one or more post-processing stages including the post-processing shader stage. The 3D pipeline may include one or more pixel shaders, one or more tile buffers, and a direct communication link between the post-processing shader stage and the one or more tile buffers. The one or more post-processing controllers may synchronize communication between the one or more post-processing shaders and the one or more tile buffers.

## Claims

### Claim 1

A graphics processing unit (GPU), comprising:
one or more post-processing controllers; and
a three-dimensional (3D) graphics pipeline including a post-processing shader stage following a pixel shader stage, wherein the one or more post-processing controllers is configured to synchronize an execution of one or more post-processing stages including the post-processing shader stage.

### Claim 2 (depends on 1)

The GPU of claim 1, further comprising:
one or more post-processing shaders;
one or more tile buffers; and
a direct communication link between the one or more post-processing shaders and the one or more tile buffers.

### Claim 3 (depends on 2)

The GPU of claim 2, wherein the one or more post-processing controllers is configured to synchronize communication between the one or more post-processing shaders and the one or more tile buffers.

### Claim 4 (depends on 2)

The GPU of claim 2, wherein the one or more post-processing shaders have access to one or more pixels from the one or more tile buffers.

### Claim 5 (depends on 4)

The GPU of claim 4, wherein the one or more pixels accessed by the one or more post-processing shaders are generated by a previous render pass for generating samples for a next render pass.

### Claim 6 (depends on 4)

The GPU of claim 4, wherein the one or more pixels are configured to be retained in a guard band residing in the one or more tile buffers responsive to the one or more post-processing controllers.

### Claim 7 (depends on 6)

The GPU of claim 6, wherein the retained one or more pixels are configured to support one or more convolution operations.

### Claim 8 (depends on 4)

The GPU of claim 4, wherein the one or more post-processing controllers is configured to retain zero pixels in a guard band.

### Claim 9

A method for performing post-processing in a graphics processing unit (GPU) in a memory-system efficient manner, comprising:
synchronizing, by one or more post-processing controllers, an execution of one or more post-processing stages in a three-dimensional (3D) graphics pipeline including a post-processing shader stage following a pixel shader stage.

### Claim 10 (depends on 9)

The method of claim 9, further comprising communicating, by a direct communication link, between the one or more post-processing shader stages and one or more tile buffers.

### Claim 11 (depends on 10)

The method of claim 10, further comprising synchronizing, by the one or more post-processing controllers, communication between the one or more post-processing shader stages and the one or more tile buffers.

### Claim 12 (depends on 10)

The method of claim 10, further comprising providing access to the one or more post-processing shader stages to one or more pixels from the one or more tile buffers.

### Claim 13 (depends on 12)

The method of claim 12, wherein the one or more pixels accessed by the one or more post-processing shader stages are generated by a previous render pass for generating samples for a next render pass.

### Claim 14 (depends on 12)

The method of claim 12, further comprising, retaining, by the one or more post-processing controllers, the one or more pixels in a guard band.

### Claim 15 (depends on 14)

The method of claim 14, further comprising supporting one or more convolution operations using the retained one or more pixels.

### Claim 16 (depends on 12)

The method of claim 12, further comprising, retaining, by the one or more post-processing controllers, zero pixels in a guard band.

### Claim 17 (depends on 9)

The method of claim 9, further comprising, querying, by an application, one or more properties of the one or more post-processing shader stages.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
querying, by the application, a tile size; and
receiving, by the application, the tile size.

### Claim 19 (depends on 9)

The method of claim 9, further comprising, interfacing, by the one or more post-processing controllers, with the application.