# US 2022/0035979 A1 · Semiconductor processing tools with improved performance by use of hybrid learning models

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- Number: US 2022/0035979 A1
- Document ID: US20220035979A1
- Status: Published application
- Kind: A1
- Application number: 16/944,012
- Filed: 2020-07-30
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Stephen Moffatt; Sheldon R. Normand; Dermot P. Cantwell
- Web page: https://patentgrep.com/patent/US20220035979A1

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.

## Claims

### Claim 1

A method for developing a semiconductor manufacturing process recipe, comprising:
selecting one or more device outcomes;
querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes, wherein the hybrid process model comprises:
a statistical model; and
a physical model;
executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model and to provide a validated process recipe; and
applying the validated process recipe to a wafer.

### Claim 2 (depends on 1)

The method of claim 1, wherein executing the DoE comprises:
measuring the DoE wafer results with a metrology tool; and
determining from the DoE wafer results if the desired device outcomes are achieved.

### Claim 3 (depends on 1)

The method of claim 1, wherein the semiconductor manufacturing process is a radical oxidation process.

### Claim 4 (depends on 3)

The method of claim 3, wherein the process recipe comprises one or more of a pressure, a temperature, a flow rate, and a soak time.

### Claim 5 (depends on 3)

The method of claim 3, wherein the device outcomes comprise one or more of a thickness, a thickness uniformity, a profile, and a hydrogen percentage.

### Claim 6 (depends on 1)

The method of claim 1, wherein the physical model is generated from a simulation of physical and chemical interactions within a processing tool across a plurality of different processing parameters.

### Claim 7 (depends on 1)

The method of claim 1, wherein the statistical model is generated from a physical DoE and interpolation of data from the physical DoE.

### Claim 8 (depends on 1)

The method of claim 1, wherein the hybrid model is a multi-dimensional process space.

### Claim 9

A method of baselining a chamber executing a semiconductor manufacturing process, comprising:
running a limited design of experiment (DoE) of wafers with external metrology to baseline chamber performance;
adding wafer outcomes and metrology data from the limited DoE to a hybrid model as a calibration data set, wherein the hybrid model comprises:
a statistical model; and
a physical model;
adjusting the model's predictions to account for specific chamber conditions and/or wafer conditions identified by the limited DoE;
predicting optimized process parameters to achieve a desired wafer outcome for wafers processed in the chamber and to provide optimized process parameters; and
applying the optimized process parameters to a wafer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the semiconductor manufacturing process is a radical oxidation process.

### Claim 11 (depends on 10)

The method of claim 10, wherein the process parameters comprises one or more of a pressure, a flow rate, temperature and a soak time.

### Claim 12 (depends on 3)

The method of claim 3, wherein the wafer outcome comprises one or more of a thickness, a thickness uniformity, a profile, and a hydrogen percentage.

### Claim 13 (depends on 9)

The method of claim 9, wherein the physical model is generated from a simulation of physical and chemical interactions within the chamber across a plurality of different processing parameters.

### Claim 14 (depends on 9)

The method of claim 9, wherein the statistical model is generated from a modeling DoE and interpolation of data from the modeling DoE.

### Claim 15 (depends on 9)

The method of claim 9, wherein the hybrid model is a multi-dimensional process space.

### Claim 16 (depends on 9)

The method of claim 9, wherein the limited DoE comprises 20 or fewer wafers.

### Claim 17

A method for processing wafers in a processing tool, comprising:
providing a hybrid model of a processing tool, wherein the hybrid model comprises:
a statistical model; and
a physical model;
executing a recipe in the processing tool to process a first wafer;
obtaining wafer data from the first wafer after execution of the recipe;
obtaining process data from the processing tool relating to the execution of the recipe;
providing the wafer data and the process data to the hybrid model to generate an updated hybrid model;
using the updated hybrid model to generate a modified recipe to account for chamber drift in the processing tool; and
applying the modified recipe to a second wafer in the processing tool.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
executing the recipe on a plurality of first wafers;
obtaining wafer data from the plurality of first wafers;
obtaining process data from the processing tool relating to the execution of the recipe on the plurality of first wafers; and
providing the wafer data and the process data from the processing of the plurality of first wafers to the hybrid model to generate an updated hybrid model.

### Claim 19 (depends on 17)

The method of claim 17, wherein the wafer data comprises metrology data.

### Claim 20 (depends on 19)

The method of claim 19, wherein the metrology data comprises one or more of a thickness, a thickness uniformity, a profile, and a hydrogen percentage.