# US 2022/0035977 A1 · Saro: scalable attack-resistant obfuscation of logic circuits

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0035977 A1
- Document ID: US20220035977A1
- Status: Published application
- Kind: A1
- Application number: 17/443,815
- Filed: 2021-07-27
- Published: 2022-02-03
- Earliest claimed: 2020-07-31
- Assignees: University of Florida Research Foundation, Inc.
- Applicants: University of Florida Research Foundation, Incorporated
- Inventors: Swarup Bhunia; Abdulrahman Alaql
- Web page: https://patentgrep.com/patent/US20220035977A1

## CPC

- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/337: Design optimisation
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.

## Claims

### Claim 1

A method of obfuscating a circuit design, the method comprising:
receiving a netlist of the circuit design;
splitting the circuit design into a plurality of partitions;
transforming each of the plurality of partitions thereby to obfuscate each partition; and
stitching the plurality of transformed partitions to form the obfuscated circuit design.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
shuffling the transformed partitions.

### Claim 3 (depends on 1)

The method of claim 1 wherein said netlist is a register transfer level netlist.

### Claim 4 (depends on 1)

The method of claim 1 further comprising:
varying a number of the plurality of partitions.

### Claim 5 (depends on 1)

The method of claim 1 further comprising:
varying a size of at least a subset of the plurality of partitions.

### Claim 6 (depends on 1)

The method of claim 1 wherein the plurality of partitions are distributed throughout an entirety of the design.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
generating a randomized circuit associated with at least a subset of each of the plurality of partitions, each randomized circuit substantially matching a shape and a size of the associated partition; and
merging each partition with the partition's associated randomized circuit.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
merging each partition with the partition's associated randomized circuit via a plurality of multiplexers each adapted to receive a different key at the multiplexer's select terminal.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
quantifying an amount of transformation associated with each partition.

### Claim 10 (depends on 1)

The method of claim 1 further comprising:
randomizing a number of outputs obfuscated in each partition.

### Claim 11 (depends on 1)

The method of claim 1 further comprising:
randomizing a location in each partition at which an obfuscation key is applied.

### Claim 12 (depends on 1)

The method of claim 1 further comprising:
randomly selecting in each partition one or more logic gates used to obfuscate the partition.

### Claim 13 (depends on 7)

The method of claim 7 further comprising:
adding a first key to at least one of the obfuscated partitions; and
adding a second key to the partition's associated randomized circuit.

### Claim 14 (depends on 7)

The method of claim 7 further comprising:
including configurable logic to enable updating of the first and second keys during various stages of development of the design.

### Claim 15

A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:
receive a netlist of the circuit design;
split the circuit design into a plurality of partitions;
transform each of the plurality of partition thereby to obfuscate each partition; and
stitch the plurality of transformed partitions to form the obfuscated circuit.

### Claim 16 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to shuffle the transformed partitions.

### Claim 17 (depends on 15)

The system of claim 15 wherein said netlist is a register transfer level netlist.

### Claim 18 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to vary a number of the plurality of partitions.

### Claim 19 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to vary a size of at least a subset of the plurality of partitions.

### Claim 20 (depends on 15)

The system of claim 15 wherein the plurality of partitions are distributed throughout an entirety of the design.

### Claim 21 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to:
generate a randomized circuit associated with at least a subset of each of the plurality of partitions, each randomized circuit substantially matching a shape and a size of the associate partition; and
merge each partition with the partition's associated randomized circuit.

### Claim 22 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to merge each partition with the partition's associated randomized circuit via a plurality of multiplexers each adapted to receive a different key at the multiplexer's select terminal.

### Claim 23 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to quantify an amount of transformation associated with each partition.

### Claim 24 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to randomize a number of outputs obfuscated in each partition.

### Claim 25 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to randomize a location in each partition at which an obfuscation key is applied.

### Claim 26 (depends on 15)

The system of claim 15 wherein the instructions further cause the processor to randomly select in each partition one or more logic gates used to obfuscate the partition.

### Claim 27 (depends on 21)

The system of claim 21 wherein the instructions further cause the processor to:
add a first key to at least one of the obfuscated partitions; and
add a second key to the partition's associated randomized circuit.

### Claim 28 (depends on 21)

The system of claim 21 wherein the instructions further cause the processor to:
include configurable logic to enable updating of the first and second keys during various stages of development of the design.