# US 2022/0035757 A1 · System for link management between multiple communication chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035757 A1 - Document ID: US20220035757A1 - Status: Published application - Kind: A1 - Application number: 17/500,325 - Filed: 2021-10-13 - Published: 2022-02-03 - Earliest claimed: 2020-01-03 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Helena Deirdre O'Shea; Camille Chen; Vijay Kumar Ramamurthi; Alon Paycher; Matthias Sauer; Bernd W. Adler - Web page: https://patentgrep.com/patent/US20220035757A1 ## CPC - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 13/3625: {using a time dependent access} - G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)} - G06F 11/3409: {for performance assessment} - G06F 13/12: using hardware independent of the central processor, e.g. channel or peripheral processor - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F 13/4068: {Electrical coupling} - G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)} - G06F 2213/0038: System on Chip - G06F 2213/40: Bus coupling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity. ## Claims ### Claim 1 A first integrated circuit, comprising: an interface circuit configured to communicate with a second integrated circuit over a multi-drop bus in an electronic device; and a processor circuit configured to: receive an authorization request from a third integrated circuit over a configurable direct connection separate from the multi-drop bus, the authorization request associated with authorization to execute an activity at the third integrated circuit, responsive at least in part to the received authorization request, determine whether the third integrated circuit is authorized to execute the activity, and responsive to the determination, send a response signal to the third integrated circuit over the configurable direct connection. ### Claim 2 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: perform, within a time limit, an internal arbitration to determine whether the third integrated circuit is authorized to execute the activity; and send, within the time limit based on the internal arbitration, the response signal to the third integrated circuit over the configurable direct connection. ### Claim 3 (depends on 1) The first integrated circuit of claim 1, wherein the received authorization request is further associated with access to a resource of the first integrated circuit for execution of the activity, and the processor circuit is further configured to: send, responsive to the determination, a grant signal or a denial signal to the third integrated circuit over the configurable direct connection to grant or deny to the third integrated circuit access to the resource. ### Claim 4 (depends on 3) The first integrated circuit of claim 3, wherein: the interface circuit is further configured to receive, from the second integrated circuit via the multi-drop bus, information about availability of the resource for a defined time period; and responsive to the received availability information, the processor circuit is further configured to send the grant signal or the denial signal to the third integrated circuit over the configurable direct connection. ### Claim 5 (depends on 1) The first integrated circuit of claim 1, wherein the processor circuit is further configured to: receive, from the third integrated circuit over the configurable direct connection, information about a priority and a persistence of the activity; and determine whether the third integrated circuit is authorized to execute the activity based in part on the received information. ### Claim 6 (depends on 1) The first integrated circuit of claim 1, wherein the received authorization request is further associated with access to a resource shared by the first integrated circuit and the third integrated circuit, and the processor circuit is further configured to: send, responsive to the determination, a grant signal or a denial signal over the configurable direct connection to the third integrated circuit to grant or deny to the third integrated circuit access to the shared resource. ### Claim 7 (depends on 6) The first integrated circuit of claim 6, wherein: the interface circuit is further configured to receive, from the second integrated circuit via the multi-drop bus, information about availability of the shared resource for a defined time period; and the processor circuit is further configured to send the grant signal or the denial signal to the third integrated circuit over the configurable direct connection in response to the received availability information. ### Claim 8 (depends on 1) The first integrated circuit of claim 1, wherein: the interface circuit is further configured to coordinate, within a time limit, with the second integrated circuit over the multi-drop bus in relation to the activity; and the processor is further configured to: perform, within the time limit, an internal arbitration in relation to the activity, determine, within the time limit based on the coordination and the internal arbitration, whether the third integrated circuit is authorized to execute the activity, and send, after the time limit based on the determination, the response signal to the third integrated circuit over the configurable direct connection. ### Claim 9 (depends on 8) The first integrated circuit of claim 8, wherein the response signal comprises a grant signal or a denial signal for granting or denying to the third integrated circuit access to a resource for execution of the activity. ### Claim 10 (depends on 8) The first integrated circuit of claim 8, wherein the response signal comprises a configuration signal for configuring at least one resource to a new state preferred for the activity requested by the third integrated circuit, the at least one resource being shared by the first integrated circuit and the third integrated circuit. ### Claim 11 A method of coordinating operations of electronic components in an electronic device at a first integrated circuit of the electronic device, the method comprising: communicating with a second integrated circuit over a multi-drop bus in the electronic device; receiving an authorization request from a third integrated circuit over a configurable direct connection separate from the multi-drop bus, the authorization request associated with authorization to execute an activity at the third integrated circuit; responsive at least in part to the received authorization request, determining whether the third integrated circuit is authorized to execute the activity; and responsive to the determination, sending a response signal to the third integrated circuit over the configurable direct connection. ### Claim 12 (depends on 11) The method of claim 11, further comprising: performing, within a time limit, an internal arbitration to determine whether the third integrated circuit is authorized to execute the activity; and sending, within the time limit based on the internal arbitration, the response signal to the third integrated circuit over the configurable direct connection. ### Claim 13 (depends on 11) The method of claim 11, wherein the received authorization request is further associated with access to a resource of the first integrated circuit for execution of the activity, and the method further comprising: sending, responsive to the determination, a grant signal or a denial signal to the third integrated circuit over the configurable direct connection to grant or deny to the third integrated circuit access to the resource; receiving, from the second integrated circuit via the multi-drop bus, information about availability of the resource for a defined time period; and responsive to the received availability information, sending the grant signal or the denial signal to the third integrated circuit over the configurable direct connection. ### Claim 14 (depends on 11) The method of claim 11, further comprising: receiving, from the third integrated circuit over the configurable direct connection, information about a priority and a persistence of the activity; and determining whether the third integrated circuit is authorized to execute the activity based in part on the received information. ### Claim 15 (depends on 11) The method of claim 11, further comprising: coordinate, within a time limit, with the second integrated circuit over the multi-drop bus in relation to the activity; performing, within the time limit, an internal arbitration in relation to the activity; determining, within the time limit based on the coordination and the internal arbitration, whether the third integrated circuit is authorized to execute the activity; and sending, after the time limit based on the determination, the response signal to the third integrated circuit over the configurable direct connection. ### Claim 16 (depends on 15) The method of claim 15, wherein sending the response signal further comprises: sending a grant signal or a denial signal to the third integrated circuit over the configurable direct connection for granting or denying to the third integrated circuit access to a resource for execution of the activity. ### Claim 17 (depends on 15) The method of claim 15, wherein sending the response signal further comprises: sending a configuration signal to the third integrated circuit over the configurable direct connection for configuring at least one resource to a new state preferred for the activity requested by the third integrated circuit, the at least one resource being shared by the first integrated circuit and the third integrated circuit. ### Claim 18 An electronic device, comprising: a multi-drop bus; and a first integrated circuit connected to a second integrated circuit via the multi-drop bus and to a third integrated circuit via a configurable direct connection separate from the multi-drop bus, the first integrated circuit configured to: receive an authorization request from the third integrated circuit over the configurable direct connection, the authorization request associated with authorization to execute an activity at the third integrated circuit, responsive at least in part to the received authorization request, determine whether the third integrated circuit is authorized to execute the activity, and responsive to the determination, send a response signal to the third integrated circuit over the configurable direct connection. ### Claim 19 (depends on 18) The electronic device of claim 18, wherein the first integrated circuit is further configured to: perform, within a time limit, an internal arbitration to determine whether the third integrated circuit is authorized to execute the activity; and send, within the time limit based on the internal arbitration, the response signal to the third integrated circuit over the configurable direct connection. ### Claim 20 (depends on 18) The electronic device of claim 18, wherein the first integrated circuit is further configured to: coordinate, within a time limit, with the second integrated circuit over the multi-drop bus in relation to the activity; perform, within the time limit, an internal arbitration in relation to the activity; determine, within the time limit based on the coordination and the internal arbitration, whether the third integrated circuit is authorized to execute the activity; and send, after the time limit based on the determination, the response signal to the third integrated circuit over the configurable direct connection.