# US 2022/0035703 A1 · Memory system including field programmable gate array (fpga) and method of operating same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035703 A1 - Document ID: US20220035703A1 - Status: Published application - Kind: A1 - Application number: 17/499,499 - Filed: 2021-10-12 - Published: 2022-02-03 - Earliest claimed: 2018-12-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: DONG-MIN SHIN; HONG-RAK SON - Web page: https://patentgrep.com/patent/US20220035703A1 ## CPC - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 7/58: Random or pseudo-random number generators - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 13/1668: {Details of memory controller} - G11C 11/409: Read-write [R-W] circuits - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/095: {Error detection codes other than CRC and single parity bit codes} - H03M 13/1105: {Decoding} - H03M 13/35: Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path. ## Claims ### Claim 1 A memory system comprising: a memory device; and a memory controller comprising a first interface, a second interface, a first data processor, and a second data processor, wherein the first data processor is configured to perform a first data processing on read data retrieved via the first interface from the memory device and output the first processed read data via one of the second interface and the second data processor, wherein the second data processor is configured to perform a second data processing on the first processed read data and output the second processed read data to an external host via the second interface, and wherein the second data processor comprises a second error correction code (ECC) engine configured to perform a second ECC decoding on the first-processed read data received from the first data processor to provide the second-processed read data. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the first data processor comprises a first ECC engine and is configured such that the read data bypasses the first ECC engine to provide the first-processed read data. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the first data processor comprises a first ECC engine configured to perform a first ECC decoding on write data received via one of the second data processor and the second interface according to a first H-matrix, and the second ECC engine performs the second ECC decoding based on a second H-matrix. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the first data processor comprises a first decryptor configured to perform a first decryption operation on the read data and to provide the first-processed read data to one of the external host via the second interface and the second data processor, and wherein the second data processor comprises a second decryptor configured to perform a second decryption operation on the first-processed read data to provide the second-processed read data to the external host via the second interface. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the first data processor comprises a first calculator configured to perform a first calculation operation having first complexity on the read data, and to provide the first-processed read data to one of the external host via the second interface and the second data processor, wherein the second data processor comprises a second calculator configured to perform a second calculation operation having second complexity on the first-processed read data, to provide the second-processed read data to the external host via the second interface, and wherein the second complexity is higher than the first complexity. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the first data processor comprises a first de-randomizer configured to perform a first de-randomization operation on the read data, and to provide the first-processed read data to one of the external host via the second interface and the second data processor, and the second data processor comprises a second de-randomizer configured to perform a second de-randomization operation on the first-processed read data received from the first data processor, and to provide the second-processed read data to the external host via the second interface. ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the first data processor is configured to perform a decompression operation on the read data, and to provide the first-processed read data to one of the external host via the second interface and the second data processor, and the second data processor is configured to perform a second decompression operation on the first-processed data received from the first data processor, and to provide the second-processed data to the external host via the second interface. ### Claim 8 (depends on 1) The memory system according to claim 1, wherein the memory controller is configured to determine whether a read operation requested by the external host is a normal read operation or a highly reliable read operation, upon determining that the read operation is the normal read operation, the memory controller configures a normal read operation path between the memory device and the external host, wherein the normal read operation path includes the first interface, the first data processor, and the second interface, upon determining that the read operation is the highly reliable read operation, the memory controller configures a highly reliable read operation path between the memory device and the external host, wherein the highly reliable read operation path includes the first interface, the first data processor, the second data processor, and the second interface. ### Claim 9 A memory system comprising: a memory device; and a memory controller comprising a first interface connected to the memory device, a second interface connected to an external host, a first data processor including a first error correction code (ECC) engine and a second data processor including a second ECC engine, wherein the memory controller is configured to determine whether a write operation requested from the external host is a normal write operation or a highly reliable write operation, upon determining that the write operation is the normal write operation, the memory controller configures a normal write operation path from the external host to the memory device, wherein the normal write operation path includes the second interface, the first data processor, and the first interface, else upon determining that the write operation is the highly reliable write operation, the memory controller configures a highly reliable write operation path from the external host to the memory device, wherein the highly reliable write operation path includes the second interface, the second data processor, the first data processor, and the first interface. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the second ECC engine is configured to generate a second ECC encoded data by performing a second ECC encoding on write data received via the second interface from the external host, upon determining that the write operation is the highly reliable write operation. ### Claim 11 (depends on 10) The memory system according to claim 10, wherein the first ECC engine is configured to perform a first ECC encoding on the second ECC encoded data received from the second data processor upon determining that the write operation is the highly reliable write operation, and wherein the first ECC engine is configured to perform the first ECC encoding on the write data received via the second interface, upon determining that the write operation is the normal write operation. ### Claim 12 (depends on 9) The memory system according to claim 9, wherein the first data processor further comprises a first encryptor configured to perform a first encryption operation on the write data received via the second interface from the external host, upon determining that the write operation is the normal write operation. ### Claim 13 (depends on 9) The memory system according to claim 9, wherein the second data processor further comprises a second encryptor configured to perform a second encryption operation on the write data received via the second interface from the external host, upon determining that the write operation is the highly reliable write operation, and the first data processor further comprises a first encryptor configured to perform a first encryption operation on the second-processed write data received from the second data processor based on the highly reliable write operation. ### Claim 14 (depends on 9) The memory system according to claim 9, wherein the first data processor further comprises a first randomizer configured to perform a first randomization operation on the write data received via the second interface from the external host, upon determining that the write operation is the normal write operation. ### Claim 15 (depends on 9) The memory system according to claim 9, wherein the second data processor further comprises a second randomizer configured to perform a second randomization operation on the write data received via the second interface from the external host, upon determining that the write operation is the highly reliable write operation, and wherein the first data processor further comprises a first randomizer configured to perform a first randomization operation on the second-processed write data received from the second data processor based on the highly reliable write operation. ### Claim 16 A method of operating a memory system comprising a field programmable gate array (FPGA), which is operated based on a program, and a memory device, the method comprising: selecting one from a normal path and a highly reliable path to write first data to the memory device; in response to selecting the highly reliable path, performing second error correction code (ECC) encoding on the first data, the second ECC encoding generating ECC parity bits varying based on the program; performing first ECC encoding on the first data having undergone the second ECC encoding; and storing the first data having undergone the first ECC encoding in the memory device according to a first writing method. ### Claim 17 (depends on 16) The method according to claim 16, wherein the performing of the second ECC encoding comprises performing the second ECC encoding based on a second H-matrix, and wherein the performing of the first ECC encoding comprises performing the first ECC encoding based on a first H-matrix that is different from the second H-matrix. ### Claim 18 (depends on 17) The method according to claim 17, further comprising: reading the first data stored in the memory device; and performing ECC decoding on the read first data based on an FPGA H-matrix comprising the first H-matrix and the second H-matrix. ### Claim 19 (depends on 16) The method according to claim 16, further comprising: changing the first writing method to a second writing method that is different from the first writing method; changing the number of ECC parity bits based on the second writing method; performing second ECC encoding on second data received from outside the memory system, the second ECC encoding generating the ECC parity bits changed in number thereof; performing the first ECC encoding on the second data having undergone the second ECC encoding; and storing the second data having undergone the first ECC encoding in the memory device according to the second writing method. ### Claim 20 (depends on 19) The method according to claim 19, wherein the first writing method is a data writing method by which n-bit data (where n is a positive integer equal to or greater than 2) is stored in each memory cell comprised in the memory device, and wherein the second writing method is a data writing method by which (n-1)-bit data is stored in each memory cell comprised in the memory device.