# US 2022/0035699 A1 · Systems and Methods for Allocating Blocks of Memory to Multiple Zones Associated with Corresponding Error Correction Mechanisms > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035699 A1 - Document ID: US20220035699A1 - Status: Published application - Kind: A1 - Application number: 17/501,890 - Filed: 2021-10-14 - Published: 2022-02-03 - Earliest claimed: 2014-12-04 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Ashish SINGHAI; Vijay KARAMCHETI; Ashwin NARASIMHA - Web page: https://patentgrep.com/patent/US20220035699A1 ## CPC - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/353: {Adaptation to the channel} - H03M 13/356: {Unequal error protection [UEP]} - G11C 2029/0411: {Online error correction} - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Systems and methods for increasing the endurance of a solid state drive are disclosed. The disclosed systems and methods can assign different levels of error protection to a plurality of blocks of the solid state drive. The disclosed methods can provide a plurality of error correction mechanisms, each having a plurality of corresponding error correction levels and associate a first plurality of blocks of the solid state drive with a first zone and a second plurality of blocks of the solid state drive with a second zone. The disclosed methods can assign a first error correction mechanism and a first corresponding error correction level to the first zone and can assign a second error correction mechanism and a second corresponding error correction level to the second zone. ## Claims ### Claim 1 A method for a data storage system, the method comprising: allocating one or more first blocks of memory to a first zone, one or more second blocks of the memory to a second zone, and one or more third blocks of the memory to a third zone; assigning a first error correction mechanism to the first zone, a second error correction mechanism to the second zone, and the second error correction mechanism to the third zone; directing one or more first command requests into the first zone and one or more second command requests into the second zone; receiving one or more third command requests, wherein the one or more third command requests are for data that is overwritten more frequently than data for the one or more second command requests; changing an error correction mechanism of the third zone by assigning the first error correction mechanism to the third zone; and directing the one or more third command requests into the third zone. ### Claim 2 (depends on 1) The method of claim 1, comprising: assigning, to the first zone, a first error correction level associated with the first error correction mechanism; and assigning, to the second zone, a second error correction level associated with the second error correction mechanism. ### Claim 3 (depends on 2) The method of claim 2, comprising: re-assigning, to the first zone, the first error correction mechanism and a third error correction level, wherein the first error correction mechanism and the third error correction level provide greater error correction than the first error correction mechanism and the first error correction level. ### Claim 4 (depends on 2) The method of claim 2, comprising: re-assigning, to the first zone, a third error correction mechanism and the first error correction level, wherein the third error correction mechanism and the first error correction level provide greater error correction than the first error correction mechanism and the first error correction level. ### Claim 5 (depends on 1) The method of claim 1, comprising: re-allocating one or more blocks of the one or more first blocks from the first zone to the second zone, when the one or more blocks have an error count greater than a threshold error count. ### Claim 6 (depends on 1) The method of claim 1, comprising: re-directing at least one command request of the one or more first command requests into the second zone, wherein the one or more first command requests are for data that is overwritten more frequently than data for the one or more second command requests. ### Claim 7 A data storage system, comprising: memory; and one or more controllers configured to cause: allocating one or more first blocks of the memory to a first zone, one or more second blocks of the memory to a second zone, and one or more third blocks of the memory to a third zone; assigning a first error correction mechanism to the first zone, a second error correction mechanism to the second zone, and the second error correction mechanism to the third zone; directing one or more first command requests into the first zone and one or more second command requests into the second zone; receiving one or more third command requests, wherein the one or more third command requests are for data that is overwritten more frequently than data for the one or more second command requests; changing an error correction mechanism of the third zone by assigning the first error correction mechanism to the third zone; and directing the one or more third command requests into the third zone. ### Claim 8 (depends on 7) The data storage system of claim 7, comprising: assigning, to the first zone, a first error correction level associated with the first error correction mechanism; and assigning, to the second zone, a second error correction level associated with the second error correction mechanism. ### Claim 9 (depends on 8) The data storage system of claim 8, comprising: re-assigning, to the first zone, the first error correction mechanism and a third error correction level, wherein the first error correction mechanism and the third error correction level provide greater error correction than the first error correction mechanism and the first error correction level. ### Claim 10 (depends on 8) The data storage system of claim 8, comprising: re-assigning, to the first zone, a third error correction mechanism and the first error correction level, wherein the third error correction mechanism and the first error correction level provide greater error correction than the first error correction mechanism and the first error correction level. ### Claim 11 (depends on 7) The data storage system of claim 7, comprising: re-allocating one or more blocks of the one or more first blocks from the first zone to the second zone, when the one or more blocks have an error count greater than a threshold error count. ### Claim 12 (depends on 7) The data storage system of claim 7, wherein the one or more controllers are configured to cause re-allocating one or more blocks of the one or more second blocks from the second zone to the first zone, when the one or more blocks have an error count less than a threshold error count. ### Claim 13 (depends on 7) The data storage system of claim 7, wherein write requests of the one or more first command requests are to generate greater write amplification than write requests of the one or more second command requests. ### Claim 14 (depends on 7) The data storage system of claim 7, wherein the memory is a multi-level cell flash device, and wherein the one or more controllers are configured to cause: dividing the multi-level cell flash device into at least one region; and assigning the first zone into the at least one region that is in a single-level cell mode. ### Claim 15 (depends on 7) The data storage system of claim 7, wherein the first zone is configured to support a greater number of program or erase cycles compared to the second zone by limiting programming to lower pages in the first zone. ### Claim 16 (depends on 7) The data storage system of claim 7, comprising: re-directing at least one command request of the one or more first command requests into the second zone, wherein the one or more first command requests are for data that is overwritten more frequently than data for the one or more second command requests. ### Claim 17 An apparatus, comprising: means for allocating one or more first blocks of memory to a first zone, one or more second blocks of the memory to a second zone, and one or more third blocks of the memory to a third zone; means for assigning a first error correction mechanism to the first zone, a second error correction mechanism to the second zone, and the second error correction mechanism to the third zone; means for directing one or more first command requests into the first zone and one or more second command requests into the second zone; means for receiving one or more third command requests, wherein the one or more third command requests are for data that is overwritten more frequently than data for the one or more second command requests; means for changing an error correction mechanism of the third zone by assigning the first error correction mechanism to the third zone; and means for directing the one or more third command requests into the third zone. ### Claim 18 (depends on 17) The apparatus of claim 17, comprising: means for assigning, to the first zone, a first error correction level associated with the first error correction mechanism; and means for assigning, to the second zone, a second error correction level associated with the second error correction mechanism. ### Claim 19 (depends on 18) The apparatus of claim 18, comprising: means for re-assigning, to the first zone, the first error correction mechanism and a third error correction level, wherein the first error correction mechanism and the third error correction level provide greater error correction than the first error correction mechanism and the first error correction level. ### Claim 20 (depends on 18) The apparatus of claim 18, comprising: means for re-assigning, to the first zone, a third error correction mechanism and the first error correction level, wherein the third error correction mechanism and the first error correction level provide greater error correction than the first error correction mechanism and the first error correction level.