# US 2022/0035649 A1 · Event notification support for nested virtual machines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035649 A1 - Document ID: US20220035649A1 - Status: Published application - Kind: A1 - Application number: 16/943,636 - Filed: 2020-07-30 - Published: 2022-02-03 - Earliest claimed: 2020-07-30 - Assignees: Red Hat, Inc. - Applicants: Red Hat, Inc. - Inventors: Michael Tsirkin; Karen Lee Noel - Web page: https://patentgrep.com/patent/US20220035649A1 ## CPC - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 9/30101: {Special purpose registers} - G06F 9/542: {Event management; Broadcasting; Multicasting; Notifications} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings} - G06F 2009/45566: {Nested virtual machines} - G06F 2009/45579: {I/O management, e.g. providing access to device drivers or storage} - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F 2212/1016: Performance improvement - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/1036: Life time enhancement - G06F 2212/151: Emulated environment, e.g. virtual machine - G06F 2212/651: Multi-level translation tables - G06F 2212/657: Virtual address space management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods for event notification support for nested virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine. The Level 1 hypervisor may generate a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, and associate the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor. The method may further responsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, cause a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address. ## Claims ### Claim 1 A method comprising: running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, generating, by the Level 1 hypervisor, a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, wherein the I/O translation table entry maps a Level 2 guest virtual address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 1 guest virtual address of a Level 1 address space associated with the Level 1 virtual machine; associating the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor; and responsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, causing a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address. ### Claim 2 (depends on 1) The method of claim 1, wherein the I/O translation table is accessible to the Level 0 hypervisor and the Level 1 hypervisor. ### Claim 3 (depends on 1) The method of claim 1, wherein the I/O translation table is stored in a model-specific register (MSR). ### Claim 4 (depends on 1) The method of claim 1, further comprising: caching, in a dedicate memory buffer, address translations that are performed by the Level 0 hypervisor associated with the I/O translation table. ### Claim 5 (depends on 1) The method of claim 1, further comprising: responsive to detecting an event notification, performing, by the Level 1 hypervisor, an address translation using the I/O translation table; and sending the address translation to the Level 0 hypervisor. ### Claim 6 (depends on 1) The method of claim 1, wherein the I/O translation table is generated in response to a configuration change event. ### Claim 7 (depends on 1) The method of claim 1, wherein the event notification comprises a signal triggered by access to a predefined I/O resource. ### Claim 8 A system, comprising: a memory; a processing device operatively coupled to the memory, the processing device configured to: run a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, generate, by the Level 1 hypervisor, a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, wherein the I/O translation table entry maps a Level 2 guest virtual address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 1 guest virtual address of a Level 1 address space associated with the Level 1 virtual machine; associate the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor; and responsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, cause a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address. ### Claim 9 (depends on 8) The system of claim 8, wherein the I/O translation table is accessible to the Level 0 hypervisor and the Level 1 hypervisor. ### Claim 10 (depends on 8) The system of claim 8, wherein the I/O translation table is stored in a model-specific register (MSR). ### Claim 11 (depends on 8) The system of claim 8, further comprising the processing device configured to: cache, in a dedicate memory buffer, address translations that are performed by the Level 0 hypervisor associated with the I/O translation table. ### Claim 12 (depends on 8) The system of claim 8, further comprising the processing device configured to: responsive to detecting an event notification, perform, by the Level 1 hypervisor, an address translation using the I/O translation table; and send the address translation to the Level 0 hypervisor. ### Claim 13 (depends on 8) The system of claim 8, wherein the I/O translation table is generated in response to a configuration change event. ### Claim 14 (depends on 8) The system of claim 8, wherein the event notification comprises a signal triggered by access to a predefined I/O resource. ### Claim 15 A non-transitory machine-readable storage medium storing executable instructions that, when executed by a processing device, cause the processing device to: run a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, generate, by the Level 1 hypervisor, a virtual device and an input/output (I/O) translation table comprising an I/O translation table entry associated with the virtual device, wherein the I/O translation table entry maps a Level 2 guest virtual address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 1 guest virtual address of a Level 1 address space associated with the Level 1 virtual machine; associate the I/O translation table entry with a Level 1 virtual machine context maintained by at least one of the Level 0 hypervisor or Level 1 hypervisor; and responsive to detecting, by the Level 0 hypervisor, an event notification from the Level 2 virtual machine, cause a central processing unit (CPU) to use the I/O translation table to execute access to the Level 1 guest virtual address. ### Claim 16 (depends on 15) The non-transitory machine-readable storage medium of claim 15, wherein the I/O translation table is accessible to the Level 0 hypervisor and the Level 1 hypervisor. ### Claim 17 (depends on 15) The non-transitory machine-readable storage medium of claim 15, wherein the I/O translation table is stored in a model-specific register (MSR). ### Claim 18 (depends on 15) The non-transitory machine-readable storage medium of claim 15, further comprising the processing device configured to: cache, in a dedicate memory buffer, address translations that are performed by the Level 0 hypervisor associated with the I/O translation table. ### Claim 19 (depends on 15) The non-transitory machine-readable storage medium of claim 15, further comprising the processing device configured to: responsive to detecting an event notification, perform, by the Level 1 hypervisor, an address translation using the I/O translation table; and send the address translation to the Level 0 hypervisor. ### Claim 20 (depends on 15) The non-transitory machine-readable storage medium of claim 15, wherein the I/O translation table is generated in response to a configuration change event.