# US 2022/0035637 A1 · On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result buffer

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- Number: US 2022/0035637 A1
- Document ID: US20220035637A1
- Status: Published application
- Kind: A1
- Application number: 16/943,525
- Filed: 2020-07-30
- Published: 2022-02-03
- Earliest claimed: 2020-07-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brian D. Barrick; Maarten J. Boersma; Niels Fricke; Dung Q. Nguyen; Brian W. Thompto; Andreas Wagner
- Web page: https://patentgrep.com/patent/US20220035637A1

## CPC

- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/30101: {Special purpose registers}
- G06F 9/3814: {Implementation provisions of instruction buffers, e.g. prefetch buffer; banks}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F 9/3873: {Variable length pipelines, e.g. elastic pipeline}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.

## Claims

### Claim 1

A method for avoiding write back collisions comprising:
receiving a plurality of instructions at a pipeline queue;
determining, by an issue queue, a number of cycles for each instruction of the plurality of instructions;
determining, by the issue queue, if a collision will occur between at least two of the instructions of the plurality of instructions;
determining, in response to a determined collision between the at least two of the instructions of the plurality of instructions, a number of cycles to delay at least one instruction of the at least two instructions;
executing the plurality of instructions;
for the at least one instruction for which a delay was determined, placing results of the at least one instruction in a result buffer for the determined number of cycles of delay;
after the determined number of cycles of delay, sending the results to a results mux; and
performing a write back process for the at least one instruction.

### Claim 2 (depends on 1)

The method of claim 1 wherein the result buffer includes a plurality of delay functions.

### Claim 3 (depends on 2)

The method of claim 2 wherein the results of the at least one instruction is placed in the result buffer at a delay function of the plurality of delay functions where a number of delay functions the at least one instruction must pass through is equal to the determined number of cycles of delay.

### Claim 4 (depends on 3)

The method of claim 3 wherein following execution of a cycle, moving the results of the at least one instruction forward one delay function within the result buffer.

### Claim 5 (depends on 3)

The method of claim 3 further comprising:
determining a number of cycles to delay a second instruction; and
placing second results of the second instruction in the result buffer for the determined number of cycles of delay.

### Claim 6 (depends on 5)

The method of claim 5 wherein following execution of a cycle, moving the results and the second results forward one delay function within the result buffer.

### Claim 7 (depends on 6)

The method of claim 6 wherein the second results are placed into the result buffer prior to moving the results of the at least one instruction forward within the result buffer.

### Claim 8 (depends on 7)

The method of claim 7 wherein when a delay function to which the results of the at least one instructions would move forward into is occupied by the second results, not moving the results of the at least one instruction forward one delay function.

### Claim 9 (depends on 1)

The method of claim 1 further comprising:
determining if a natural pipe is available for the plurality of instructions; and
in response to the natural pipe being available, implementing no delay for the plurality of instructions.

### Claim 10

A system for avoiding a write back collision in a register file, comprising:
a pipeline queue configured to manage a plurality of instructions processed through at least two pipes;
a result buffer, separate from the at least two pipes, configured to delay processing of results for at least one of the plurality of instructions; and
a write back port to write back results of the plurality of instructions to the register file, wherein the write back port is configured to receive results from the results buffer and the at least two pipes.

### Claim 11 (depends on 10)

The system of claim 10 wherein the pipeline queue further comprises:
an issue queue configured to:
determine a number of cycles for each instruction of the plurality of instructions;
determine if a collision will occur between at least two of the instructions of the plurality of instructions; and
determine in response to a determined collision between at least two of the instructions of the plurality of instructions, a number of cycles to delay at least one of the at least two of the instructions.

### Claim 12 (depends on 10)

The system of claim 10 wherein the result buffer includes a plurality of delay points.

### Claim 13 (depends on 12)

The system of claim 12 wherein a result in the result buffer moves from a first delay point to a second delay point following execution of a cycle by the system.

### Claim 14 (depends on 13)

The system of claim 13 wherein the result buffer does not move rfesults from the first delay point to the second delay point when the second delay point includes a newly placed result.

### Claim 15 (depends on 12)

The system of claim 12 wherein a result is placed into the result buffer at a delay point of the plurality of delay points such that a number of delay points in front of the results is equal to a calculated number of cycles of delay determined to avoid a write back collision.

### Claim 16

A computer readable storage medium configured for avoiding write back collisions having computer executable instructions that when executed cause a computing system to perform a method of:
receiving a plurality of instructions at a pipeline queue;
determining, by an issue queue, a number of cycles for each instruction of the plurality of instructions;
determining, by the issue queue, if a collision will occur between at least two of the instructions of the plurality of instructions;
determining, in response to a determined collision between the at least two of the instructions of the plurality of instructions, a number of cycles to delay at least one instruction of the at least two instructions;
executing the plurality of instructions;
for the at least one instruction for which a delay was determined, placing results of the at least one instruction in a result buffer for the determined number of cycles of delay;
after the determined number of cycles of delay, sending the results to a results mux; and
performing a write back process for the at least one instruction.

### Claim 17 (depends on 16)

The computer readable storage medium of claim 16 wherein the result buffer includes a plurality of delay functions.

### Claim 18 (depends on 17)

The computer readable storage medium of claim 17 wherein the results of the at least one instruction is placed in the result buffer at a delay function of the plurality of delay functions where a number of delay functions the results of the at least one instruction must pass through is equal to the determined number of cycles of delay.

### Claim 19 (depends on 18)

The computer readable storage medium of claim 18 wherein following execution of a cycle, moving the results of the at least one instruction forward one delay function within the result buffer.

### Claim 20 (depends on 17)

The computer readable storage medium of claim 17 further comprising:
determining a number of cycles to delay a second instruction; and
placing second results of the second instruction in the result buffer for the determined number of cycles of delay.