# US 2022/0035634 A1 · Microprocessor that fuses load and compare instructions

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- Number: US 2022/0035634 A1
- Document ID: US20220035634A1
- Status: Published application
- Kind: A1
- Application number: 16/941,969
- Filed: 2020-07-29
- Published: 2022-02-03
- Earliest claimed: 2020-07-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bryan Lloyd; David A. Hrusecky; Sundeep Chadha; Dung Q. Nguyen; Christian Gerhard Zoellin; Brian W. Thompto; Sheldon Bernard Levenstein; Phillip G. Williams
- Web page: https://patentgrep.com/patent/US20220035634A1

## CPC

- G06F 9/30181: {Instruction operation extension or modification}
- G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30094: {Condition code generation, e.g. Carry, Zero flag}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3867: {using instruction pipelines}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

## Claims

### Claim 1

A computer-implemented method (CIM) comprising:
receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value;
receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value;
determining, by the instruction fetch unit, that the RT field value is the same as the RA field value;
responsive to the determination that the RA field value is the same as the RT field value, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction; and
generating an early compare result to provide a condition code representing an answer to a compare earlier to a dependent branch instruction so that the dependent branch instruction can determine whether a given branch should have been taken.

### Claim 2 (depends on 1)

The CIM of claim 1 wherein the load instruction and the compare-immediate instruction are consecutive instructions.

### Claim 3 (depends on 1)

The CIM of claim 1 further comprising:
determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1;
wherein the fusion is further responsive to the determination that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1.

### Claim at position 4

4-17. (canceled)

### Claim 18

A computer-implemented method (CIM) comprising:
receiving, by an instruction fetch unit of a load-store architecture style processor, a load instruction including an RT field value;
receiving, by the instruction fetch unit, a compare-immediate instruction including an RA field value;
determining that the load instruction and the compare-immediate instruction are consecutive instructions;
determining, by the instruction fetch unit, that an immediate field of the compare-immediate instruction has a value that falls within a predetermined range of values;
responsive to the determination that the load instruction and the compare-immediate instruction are consecutive instructions and further responsive to the determination that that an immediate field of the compare-immediate instruction has a value that falls within a predetermined range of values, fusing, by the instruction fetch unit, the load instruction and the compare-immediate instruction to form a single fused instruction; and
generating an early compare result to provide a condition code representing an answer to a compare earlier to a dependent branch instruction so that the dependent branch instruction can determine whether a given branch should have been taken.

### Claim 19 (depends on 18)

The CIM of claim 18 wherein the range of predetermined values is 0, or −1.

### Claim 20 (depends on 18)

The CIM of claim 18 further comprising:
wherein the fusion is further responsive to the determination that an immediate field of the compare-immediate instruction has a value of 0, 1, or −1.