# US 2022/0035633 A1 · Method and Apparatus for Back End Gather/Scatter Memory Coalescing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035633 A1 - Document ID: US20220035633A1 - Status: Published application - Kind: A1 - Application number: 16/944,146 - Filed: 2020-07-30 - Published: 2022-02-03 - Earliest claimed: 2020-07-30 - Assignees: Marvell Asia Pte Ltd - Applicants: Marvell Asia Pte, Ltd. - Inventors: Harold Wade Cain, III; Nagesh Bangalore Lakshminarayana; Daniel Jonathan Ernst; Sanyam Mehta - Web page: https://patentgrep.com/patent/US20220035633A1 ## CPC - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/30181: {Instruction operation extension or modification} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/546: {Message passing systems or structures, e.g. queues} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses. ## Claims ### Claim 1 A system for processing gather and scatter instructions, comprising: a load-store unit configured to 1) receive a plurality of access operations corresponding to an instruction, the instruction being one of a scatter instruction and a gather instruction, 2) determine a subset of the plurality of access operations that can be coalesced, and 3) form a coalesced memory access operation from the subset; and a queue configured to store multiple memory addresses for a given load-store entry, the load-store unit configured to load an entry corresponding to the coalesced memory access operation to the queue, the entry indicating addresses of each of the subset. ### Claim 2 (depends on 1) The system of claim 1, wherein the load-store unit is further configured to determine a minimum quantity of cache accesses required for the instruction based on the plurality of access operations. ### Claim 3 (depends on 2) The system of claim 2, wherein the load-store unit is further configured to reserve a number of operational cycles corresponding to the minimum number of cache accesses. ### Claim 4 (depends on 3) The system of claim 3, wherein the load-store unit is further configured to execute the coalesced memory access operation via a memory access lane over the number of operational cycles. ### Claim 5 (depends on 1) The system of claim 1, further comprising a decode unit configured to 1) convert the instruction into the plurality of access operations, and 2) transmit the plurality of access operations to the load-store unit. ### Claim 6 (depends on 5) The system of claim 5, wherein decode unit is further configured to transmit to the load-store unit an indication of a predicted quantity of coalesced memory access operations required by the instruction. ### Claim 7 (depends on 6) The system of claim 6, wherein the load-store unit is further configured to 1) determine an actual quantity of coalesced memory accesses required by the instruction, 2) provide an indication of the actual quantity to a prediction unit. ### Claim 8 (depends on 7) The system of claim 7, wherein the prediction unit is further configured to update a table based on the predicted quantity and the actual quantity. ### Claim 9 (depends on 7) The system of claim 7, wherein the load-store unit is further configured to determine a misprediction based on a comparison of the predicted quantity and the actual quantity of coalesced memory access operations required by the instruction. ### Claim 10 (depends on 1) The system of claim 1, wherein the load-store unit analyzes a portion of the plurality of access operations to determine the subset of the plurality of access operations that can be coalesced. ### Claim 11 (depends on 1) The system of claim 1, wherein the load-store unit is further configured to 1) assign the coalesced memory access operation to at least one memory access lane, and 2) execute the coalesced memory access operation via the memory access lane. ### Claim 12 A method of processing gather and scatter instructions, comprising: receiving a plurality of access operations corresponding to an instruction, the instruction being one of a scatter instruction and a gather instruction; determining a subset of the plurality of access operations that can be coalesced; forming a coalesced memory access operation from the subset; storing multiple memory addresses for a given load-store entry to a queue; and loading an entry corresponding to the coalesced memory access operation to the queue, the entry indicating addresses of each of the subset. ### Claim 13 (depends on 12) The method of claim 12, further comprising determining a minimum quantity of cache accesses required for the instruction based on the plurality of access operations. ### Claim 14 (depends on 13) The method of claim 13, further comprising reserving a number of operational cycles corresponding to the minimum number of cache accesses. ### Claim 15 (depends on 14) The method of claim 14, further comprising executing the coalesced memory access operation via a memory access lane over the number of operational cycles. ### Claim 16 (depends on 12) The method of claim 12, further comprising: converting the instruction into the plurality of access operations; and transmitting the plurality of access operations to a load-store unit. ### Claim 17 (depends on 16) The method of claim 16, further comprising transmitting to the load-store unit an indication of a predicted quantity of coalesced memory access operations required by the instruction. ### Claim 18 (depends on 17) The method of claim 17, further comprising: determining an actual quantity of coalesced memory accesses required by the instruction; and providing an indication of the actual quantity to a prediction unit. ### Claim 19 (depends on 18) The method of claim 18, further comprising updating a table based on the predicted quantity and the actual quantity. ### Claim 20 (depends on 18) The method of claim 18, further comprising determining a misprediction based on a comparison of the predicted quantity and the actual quantity of coalesced memory access operations required by the instruction. ### Claim 21 (depends on 15) The method of claim 15, further comprising analyzing a portion of the plurality of access operations to determine the subset of the plurality of access operations that can be coalesced. ### Claim 22 (depends on 15) The method of claim 15, further comprising assigning the coalesced memory access operation to at least one memory access lane; and executing the coalesced memory access operation via the memory access lane.