# US 2022/0035631 A1 · Handling oversize store to load forwarding in a processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035631 A1 - Document ID: US20220035631A1 - Status: Published application - Kind: A1 - Application number: 16/943,408 - Filed: 2020-07-30 - Published: 2022-02-03 - Earliest claimed: 2020-07-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Bryan Lloyd; Brian Chen; Kimberly M. Fernsler; Robert A. Cordes; David A. Hrusecky - Web page: https://patentgrep.com/patent/US20220035631A1 ## CPC - G06F 9/3834: {Maintaining memory consistency} - G06F 9/34: Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} - G06F 9/3824: {Operand accessing} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract System includes at least one computer processor having a load store execution unit (LSU) for processing load and store instructions, wherein the LSU includes (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a width for storing the data; and (b) a gather buffer for holding data, wherein the processor is configured to: process oversize data larger than the width of the data field of the store queue, and process an oversize load instruction for oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data. ## Claims ### Claim 1 A computer system for processing information, the computer system comprising: at least one computer processor comprising: a load store execution unit (LSU) for processing load and store instructions, wherein the LSU comprises: a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a maximum width for storing the data; and a gather buffer for holding data; wherein the at least one computer processor is configured to: process oversize data larger than the maximum width of the data field of the store queue, process an oversize load instruction for the oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the at least one computer processor is further configured to store the oversize data in at least two consecutive entries in the store queue. ### Claim 3 (depends on 2) The computer system of claim 2, wherein the at least one computer processor is further configured so that the data field of the store queue is half a size of the oversize data capable of being processed by the at least one computer processor, the at least one computer processor configured to simultaneously store the oversize data in at least two entries in the store queue. ### Claim 4 (depends on 1) The computer system of claim 1, wherein the at least one computer processor is further configured to: obtain a copy of the first portion of the oversize data from a first entry of the plurality of entries in the store queue during a first pass through the LSU; and move the copy of the first portion of the oversize data to the gather buffer during the first pass through the LSU. ### Claim 5 (depends on 4) The computer system of claim 4, wherein the at least one computer processor is further configured to: obtain a copy of the second portion of the oversize data from a second entry of the plurality of entries in the store queue during a second pass through the LSU; and merge during the second pass through the LSU the copy of the second portion of the oversize data with the first portion of the oversize data from the gather buffer. ### Claim 6 (depends on 1) The computer system of claim 1, wherein the LSU further comprises a Load Launch Queue (LLQ), the LLQ having circuitry and logic for tracking and controlling load operations in the LSU, the LLQ configured to control the two passes through the LSU. ### Claim 7 (depends on 1) The computer system of claim 1, wherein the at least one computer processor is further configured to: detect the oversize load instruction for the oversize data that is larger than the maximum width of the data field in the store queue; and determine, in response to detecting the oversize load instruction, whether the store queue contains any of the oversize data. ### Claim 8 (depends on 7) The computer system of claim 7, wherein the at least one computer processor is further configured to: determine, in response to the store queue containing any of the oversize data, whether a first store queue entry in the plurality of entries contains all of the first portion of the oversize data; and obtain, in response to the first store queue entry containing all of the first portion of the oversize data, the first portion of the oversize data from the first store queue entry. ### Claim 9 (depends on 8) The computer system of claim 8, wherein the at least one computer processor is further configured to: determine whether a second store queue entry of the plurality of entries contains all of the second portion of the oversize data; and obtain, in response to the second store queue entry containing all of the second portion of the oversize data, the second portion of the oversize data from the second store queue entry. ### Claim 10 (depends on 7) The computer system of claim 7, wherein the at least one computer processor is further configured to compare memory address information in each of the store queue entries with the memory address contained within the oversize load to determine whether any store queue entry contains any of the oversize data. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the at least one computer processor is further configured to determine whether a store start address and a store end address of each store queue entry falls within an oversize load start address and an oversize load end address range of the oversize load instruction to determine whether any store queue entry contains any of the oversize data. ### Claim 12 (depends on 8) The computer system of claim 8, wherein the at least one computer processor is further configured to: compare memory address information in each of the plurality of entries to a first half of a memory address contained in the oversize load instruction to determine whether the first store queue entry contains all of the first portion of the oversize data; and compare memory address information in each of the plurality of entries to a second half of the memory address contained in the oversize load instruction to determine whether a second store queue entry contains all of the second portion of the oversize data. ### Claim 13 A method of processing data in a processor, comprising: detecting an oversize load instruction for oversize data that is larger than a width of a data field in a store queue; determining, in response to detecting the oversize load instruction, whether the store queue contains any of the oversize data; determining, in response to the store queue containing any of the oversize data, whether a first store queue entry contains all of a first portion of the oversize data; obtaining, in response to the first store queue entry containing all of a first portion of the oversize data, the first portion of the oversize data from the first store queue entry; storing the first portion of the oversize data from the first store queue entry into a gather buffer; and merging the first portion of the oversize data from the gather buffer with a second portion of the oversize data, wherein the first portion of the oversize data is obtained from the store queue by a first pass through a load store unit (LSU) and the second portion of the oversize data is obtained by a second pass through the LSU. ### Claim 14 (depends on 13) The method according to claim 13, wherein merging the first portion of the oversize data from the gather buffer with the second portion of the oversize data further comprises: determining whether a second store queue entry contains all of the second portion of the oversize data; and obtaining, in response to the second store queue entry containing all of the second portion of the oversize data, the second portion of the oversize data from the second store queue entry. ### Claim 15 (depends on 13) The method according to claim 13, wherein in response to determining that all of one of the first portion or the second portion of the oversize data is not in a store queue entry, obtaining all of the first portion or the second portion of the oversize data that is not in a store queue entry from a data cache. ### Claim 16 (depends on 13) The method according to claim 13, wherein determining whether the store queue contains any of the oversize data includes comparing memory address information in each store queue entry with a memory address referred to in the oversize load instruction. ### Claim 17 (depends on 16) The method according to claim 16, wherein comparing the memory address information in each store queue entry with the memory address referred to in the oversize load instruction includes determining whether a store start address and a store end address in each store queue entry falls within an oversize load start address and an oversize load end address range of the oversize load instruction. ### Claim 18 (canceled) ### Claim 19 (depends on 13) The method of claim 13, further comprising simultaneously storing oversize data in two consecutive store queue entries. ### Claim 20 A computer system for processing information, the computer system comprising: at least one processor; a load store execution unit (LSU) for processing load and store instructions, the LSU comprising (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing data, the data field having a width for storing data, (b) a gather buffer for holding data, and (c) a Load Launch Queue (LLQ) for managing and controlling load instructions in the store queue; one or more computer readable non-transitory storage media; and programming instructions stored on the one or more computer readable non-transitory storage media for execution by the at least one processor, the programming instructions comprising: programming instructions to process oversize data larger than the maximum width of the data field of the store queue; programming instructions to store the oversize data in at least two consecutive entries in the store queue; and programming instructions to process an oversize load instruction for the oversize data by executing two passes through the LSU, a first pass through the LSU to store a first half of the oversize data in the gather buffer and a second pass through the LSU to merge the first half of the oversize data from the gather buffer with a second half of the oversize data obtained by the second pass through the LSU.