# US 2022/0035607 A1 · Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2022/0035607 A1 - Document ID: US20220035607A1 - Status: Published application - Kind: A1 - Application number: 17/500,509 - Filed: 2021-10-13 - Published: 2022-02-03 - Earliest claimed: 2019-05-23 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Akella Sastry; Vinod K. Kathail; L. James Hwang; Shail Aditya Gupta; Vidhumouli Hunsigida; Siddharth Rele - Web page: https://patentgrep.com/patent/US20220035607A1 ## CPC - G06F 8/41: Compilation - G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package} - G06F 8/447: {Target code generation} - G06F 30/343: Logical level - H03K 19/17724: Structural details of logic blocks - G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip} - G06F 15/7867: {with reconfigurable architecture} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 A method of implementing an application within an integrated circuit having a data processing engine array coupled to a Network-on-Chip (NoC), the method comprising: determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the data processing engine array by simulating data traffic to the NoC as generated by the software portion; generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion; compiling the software portion of the application for execution by different ones of a plurality of data processing engines of the data processing engine array based, at least in part, on the NoC routing solution; and generating, using the computer hardware, configuration data that, when loaded into the integrated circuit, configures the NoC to implement the NoC routing solution. ### Claim 22 (depends on 21) The method of claim 21, wherein a data processing engine compiler determines the data traffic requirements for the software portion and provides the data traffic requirements to a NoC compiler. ### Claim 23 (depends on 22) The method of claim 22, wherein the NoC compiler provides the routing solution to the data processing engine compiler, and wherein the data processing engine compiler compiles the software portion of the application. ### Claim 24 (depends on 21) The method of claim 21, comprising: determining data traffic requirements for a hardware portion of the application intended for implementation in programmable logic of the integrated circuit; and generating the NoC routing solution based, at least in part, on the data traffic requirements for the hardware portion. ### Claim 25 (depends on 21) The method of claim 21, wherein the application is simulated based on a logical architecture of the application, wherein the logical architecture defines, at least in part, connections of the application between the data processing engine array and other circuitry of the integrated circuit that are routed through the NoC. ### Claim 26 (depends on 21) The method of claim 21, wherein the routing solution specifies ingress points and egress points for the data paths for the NoC. ### Claim 27 (depends on 21) The method of claim 21, comprising: determining connectivity between a plurality of nodes of the software portion to be executed by different ones of the plurality of data processing engines and one or more high-level synthesis kernels of a hardware portion of the application to be implemented in programmable logic of the integrated circuit; and wherein the software portion of the application is compiled based, at least in part, on the connectivity between the plurality of nodes and the one or more high-level synthesis kernels. ### Claim 28 A system for implementing an application within an integrated circuit having a data processing engine array coupled to a Network-on-Chip (NoC), the system comprising: one or more processors configured to initiate operations including: determining data transfer requirements for a software portion of the application intended to execute on the data processing engine array by simulating data traffic to the NoC as generated by the software portion; generating a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion; compiling the software portion of the application for execution by different ones of a plurality of data processing engines of the data processing engine array based, at least in part, on the NoC routing solution; and generating configuration data that, when loaded into the integrated circuit, configures the NoC to implement the NoC routing solution. ### Claim 29 (depends on 28) The system of claim 28, wherein a data processing engine compiler executed by the one or more processors determines the data traffic requirements for the software portion and provides the data traffic requirements to a NoC compiler executed by the one or more processors. ### Claim 30 (depends on 29) The system of claim 29, wherein the NoC compiler provides the routing solution to the data processing engine compiler, and wherein the data processing engine compiler compiles the software portion of the application. ### Claim 31 (depends on 28) The system of claim 28, wherein the one or more processors are configured to initiate operations comprising: determining data traffic requirements for a hardware portion of the application intended for implementation in programmable logic of the integrated circuit; and generating the NoC routing solution based, at least in part, on the data traffic requirements of the hardware portion. ### Claim 32 (depends on 28) The system of claim 28, wherein the application is simulated based on a logical architecture of the application, wherein the logical architecture defines, at least in part, connections of the application between the data processing engine array and other circuitry of the integrated circuit that are routed through the NoC. ### Claim 33 (depends on 28) The system of claim 28, wherein the routing solution specifies ingress points and egress points for the data paths for the NoC. ### Claim 34 (depends on 28) The system of claim 28, wherein the one or more processors are configured to initiate operations comprising: determining connectivity between a plurality of nodes of the software portion to be executed by different ones of the plurality of data processing engines and one or more high-level synthesis kernels of a hardware portion of the application to be implemented in programmable logic of the integrated circuit; and wherein the software portion of the application is compiled based, at least in part, on the connectivity between the plurality of nodes and the one or more high-level synthesis kernels. ### Claim 35 A computer program product, comprising: one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, wherein the program instructions are executable by computer hardware to initiate operations for implementing an application within an integrated circuit having a data processing engine array coupled to a Network-on-Chip (NoC), the operations including: determining data transfer requirements for a software portion of the application intended to execute on the data processing engine array by simulating data traffic to the NoC as generated by the software portion; generating a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion; compiling the software portion of the application for execution by different ones of a plurality of data processing engines of the data processing engine array based, at least in part, on the NoC routing solution; and generating configuration data that, when loaded into the integrated circuit, configures the NoC to implement the NoC routing solution. ### Claim 36 (depends on 35) The computer program product of claim 35, wherein a data processing engine compiler determines the data traffic requirements for the software portion and provides the data traffic requirements to a NoC compiler; and wherein the NoC compiler provides the routing solution to the data processing engine compiler, and wherein the data processing engine compiler compiles the software portion of the application. ### Claim 37 (depends on 35) The computer program product of claim 35, wherein the program instructions are executable by computer hardware to initiate operations including: determining data traffic requirements for a hardware portion of the application intended for implementation in programmable logic of the integrated circuit; and generating the NoC routing solution based, at least in part, on the data traffic requirements of the hardware portion. ### Claim 38 (depends on 35) The computer program product of claim 35, wherein the application is simulated based on a logical architecture of the application, wherein the logical architecture defines, at least in part, connections of the application between the data processing engine array and other circuitry of the integrated circuit that are routed through the NoC. ### Claim 39 (depends on 35) The computer program product of claim 35, wherein the routing solution specifies ingress points and egress points for the data paths for the NoC. ### Claim 40 (depends on 35) The computer program product of claim 35, wherein the program instructions are executable by computer hardware to initiate operations including: determining connectivity between a plurality of nodes of the software portion to be executed by different ones of the plurality of data processing engines and one or more high-level synthesis kernels of a hardware portion of the application to be implemented in programmable logic of the integrated circuit; and wherein the software portion of the application is compiled based, at least in part, on the connectivity between the plurality of nodes and the one or more high-level synthesis kernels.