# US 2022/0035239 A1 · Method of manufacturing a membrane assembly

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2022/0035239 A1
- Document ID: US20220035239A1
- Status: Published application
- Kind: A1
- Application number: 17/278,356
- Filed: 2019-10-02
- Published: 2022-02-03
- Earliest claimed: 2018-10-15
- Assignees: ASML Netherlands B.V.
- Applicants: Asml Netherlands B.V.
- Inventors: Pieter-Jan VAN ZWOL; Sander BALTUSSEN; Dennis DE GRAAF; Johannes Christiaan Leonardus FRANKEN; Adrianus Johannes Maria GIESBERS; Alexander Ludwig KLEIN; Johan Hendrik KLOOTWIJK; Peter Simon Antonius KNAPEN; Evgenia KURGANOVA; Alexey Sergeevich KUZNETSOV; Arnoud Willem NOTENBOOM; Mahdiar VALEFI; Marcus Adrianus VAN DE KERKHOF; Wilhelmus Theodorus Anthonius Johannes VAN DEN EINDEN; Ties Wouter VAN DER WOORD; Hendrikus Jan WONDERGEM; Aleksandar Nikolov ZDRAVKOV
- Web page: https://patentgrep.com/patent/US20220035239A1

## CPC

- G03F 1/62: Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
- G03F 1/64: characterised by the frames, e.g. structure or material, including bonding means therefor
- G03F 7/7015: {Details of optical elements}
- G03F 7/70191: {Optical correction elements, filters or phase plates for controlling intensity, wavelength, polarisation, phase or the like}
- G03F 7/70308: {Optical correction elements, filters or phase plates for manipulating imaging light, e.g. intensity, wavelength, polarisation, phase or image shift}
- G03F 7/70916: {Pollution mitigation, i.e. mitigating effect of contamination or debris, e.g. foil traps}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

A method for manufacturing a membrane assembly for EUV lithography, the method including: providing a stack including: at least one membrane layer supported by a planar substrate, wherein the planar substrate has an inner region and a border region around the inner region; and a first sacrificial layer between the planar substrate and the membrane layer; selectively removing the inner region of the planar substrate such that the membrane assembly has: a membrane formed from the at least one membrane layer, and a border holding the membrane, the border having the border region of the planar substrate and the first sacrificial layer situated between the border region and the membrane layer, wherein the selectively removing the inner region of the planar substrate includes using an etchant which has a similar etch rate for the membrane layer and its oxide and a substantially different etch rate for the first sacrificial layer.

## Claims

### Claim 1

A membrane assembly for EUV lithography, the membrane assembly comprising:
a membrane formed from at least one membrane layer comprising polycrystalline silicon or monocrystalline silicon; and
a border holding the membrane,
wherein the border is formed from a planar substrate comprising an inner region and a border region around the inner region,
wherein the border resulted from selective removal of the inner region of the planar substrate,
wherein the planar substrate comprises a core layer and a sacrificial layer such that the border comprises the core layer and the sacrificial layer,
wherein the sacrificial layer is between the core layer and the at least one membrane layer, and
wherein an etch rate of an etchant of the core layer and the at least one membrane layer is substantially different to the etch rate of an etchant of the sacrificial layer.

### Claim 2 (depends on 1)

The membrane assembly of claim 1, wherein the sacrificial layer comprises silicon nitride.

### Claim 3 (depends on 1)

The membrane assembly of claim 1, wherein the core layer comprises silicon.

### Claim 4 (depends on 1)

The membrane assembly of claim 1, wherein the core layer and the at least one membrane layer comprise silicon.

### Claim 5 (depends on 1)

The membrane assembly of claim 1, wherein the etch rate of the core layer and the at least one membrane layer is substantially less than the etch rate of the sacrificial layer.

### Claim 6 (depends on 5)

The membrane assembly of claim 5, wherein the etchant comprises phosphoric acid.

### Claim 7 (depends on 1)

The membrane assembly of claim 1, wherein the membrane assembly is for a patterning device or a dynamic gas lock.

### Claim 8 (depends on 1)

The membrane assembly of claim 1, wherein the membrane assembly comprises a ruthenium-based capping layer.

### Claim 9 (depends on 8)

The membrane assembly of claim 8, wherein the ruthenium-based capping layer is arranged on a molybdenum layer.

### Claim 10 (depends on 9)

The membrane assembly of claim 9, wherein the molybdenum layer is arranged on the core layer.

### Claim 11 (depends on 9)

The membrane assembly of claim 9, further comprising a Ru/Mo intermixing layer at an interface of the molybdenum layer and the ruthenium-based capping layer.

### Claim 12 (depends on 11)

The membrane assembly of claim 11, further comprising multiple Ru/Mo intermixing layers.

### Claim 13

A method for manufacturing a membrane assembly for EUV lithography, the method comprising:
providing a stack comprising:
at least one membrane layer supported by a planar substrate, wherein the planar substrate comprises an inner region and a border region around the inner region; and
a first sacrificial layer between the planar substrate and the membrane layer;
selectively removing the inner region of the planar substrate such that the membrane assembly comprises: a membrane formed from the at least one membrane layer, and a border holding the membrane, the border comprising the border region of the planar substrate and the first sacrificial layer situated between the border region and the membrane layer,
wherein the selectively removing the inner region of the planar substrate comprises using an etchant which has a similar etch rate for the membrane layer and its oxide and a substantially different etch rate for the first sacrificial layer.

### Claim 14 (depends on 13)

The method according to claim 13, further comprising providing a resist on the stack and patterning the resist prior to the selectively removing the inner region.

### Claim 15 (depends on 1)

A lithographic apparatus comprising the membrane assembly according to claim 1.

### Claim 16

An optical element for a lithographic apparatus, the optical element including a stack that comprises a core, a capping layer, and an oxygen barrier layer between the capping layer and the core.

### Claim 17 (depends on 16)

The optical element according to claim 16, wherein the oxygen barrier layer includes at least one silicon oxide layer and at least one zirconium oxide or yttrium oxide layer.

### Claim 18 (depends on 16)

The optical element according to claim 16, wherein the oxygen barrier layer includes a zirconium silicon oxide layer or an yttrium silicon oxide layer.

### Claim 19 (depends on 16)

The optical element according to claim 16, wherein the optical element also includes an IR-suppression layer.

### Claim 20 (depends on 16)

The optical element according to claim 16, wherein the core comprises two sides, and wherein an oxygen barrier layer is disposed between each side of the core and a respective capping layer on each side of the core.