Capacitor voltage stacking pipeline analog-to-digital converter (adc)

A method comprising:

• sampling, by an ADC sub-circuit stage, a differential input signal;
• comparing, by a comparator of the ADC sub-circuit stage, each path of the sampled differential input signal;
• if a voltage of the sampled differential input signal is determined to be positive:
• opening a set of capacitor switches;
• setting a reference voltage switch to apply a negative reference voltage to the set of capacitors;
• output a residual analog signal;
• and
• output a logic ‘1’ as a digital value of an associated bit position;
• and
• if a voltage of the sampled differential input signal is determined to be negative:
• opening a set of capacitor switches;
• setting a reference voltage switch to apply a positive reference voltage to the set of capacitors;
• and
• output a residual analog signal;
• and
• output a logic ‘0’ as a digital value of an associated bit position.

A pipelined ADC circuit comprising:

• a plurality of stages disposed such that an output of a previous stage is an input of a subsequent stage, each of the stages comprising:
• a differential input configured to receive a differential signal comprising a positive voltage signal on a first path and a negative voltage signal on a second path;
• a multiplying digital-to-analog converter (MDAC) electrically coupled to the differential input configured to stack voltages of a set of capacitors;
• a comparator electrically coupled to the first path and the second path and electrically disposed after the MDAC, a first input of the comparator connected to the first path and a second input of the comparator connected to the second path;
• and
• a source follower buffer electrically coupled to the first path and the second path and electrically disposed after the comparator,
• wherein the MDAC is configured to amplify an output voltage using passive multiplication;
• and
• an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages,
• wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.