SUB-ADC Assignment in TI-ADC

Abstract

A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M≥2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak1) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (Ak2) in a second subset of the group of sub-ADCs (A1-AM+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.

Dependencies are inferred from the claim text.