US 2022/0029630 A1Published application

Method and apparatus for performing on-system phase-locked loop management in memory device

AssigneeSilicon Motion, Inc.

InventorFu-Jen Shih

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Claims10

Dependent claims

A method for performing on-system phase-locked loop (PLL) management in a memory device, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the method comprising:

utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit, wherein the transmission interface circuit comprises a physical layer (PHY) circuit, and the PHY circuit comprises the PLL, a trimming control circuit and the register circuit, wherein a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO), and the trimming control circuit is arranged to perform trimming control on the PLL, for supporting optimization of the PLL that uses the VCXO, wherein the optimization of the PLL comprises parameter adjustment of the PLL;
utilizing the trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of the VCO, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage;
and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management of the memory device.

1 more element

A memory device, comprising:

a non-volatile (NV) memory, arranged to store information, wherein the NV memory comprises at least one NV memory element;
and
a controller, coupled to the NV memory, arranged to control operations of the memory device, wherein the controller comprises:
a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
and
a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
a physical layer (PHY) circuit, comprising:
a phase-locked loop (PLL), wherein a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO);
a trimming control circuit, arranged to perform trimming control on the PLL, for supporting optimization of the PLL that uses the VCXO, wherein the optimization of the PLL comprises parameter adjustment of the PLL;
and
a register circuit, arranged to store multiple parameters of the PLL, and store multiple processing results of the parameter adjustment of the PLL, wherein the multiple parameters comprise multiple control parameters;
wherein:
the controller utilizes the processing circuit to set the multiple control parameters, for controlling the parameter adjustment of the PLL;
the controller utilizes the trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of the VCO, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage;
and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, the controller utilizes the trimming control circuit to generate and store the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving on-system PLL management of the memory device.

13 more elements

A controller of a memory device, the memory device comprising the controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the controller comprising:

a processing circuit, arranged to control the controller according to a plurality of host commands from a host device, to allow the host device to access the NV memory through the controller;
and
a transmission interface circuit, coupled to the processing circuit, arranged to perform communications with the host device, wherein the transmission interface circuit comprises:
a physical layer (PHY) circuit, comprising:
a phase-locked loop (PLL), wherein a voltage controlled oscillator (VCO) in the PLL is implemented with a voltage controlled crystal oscillator (VCXO);
a trimming control circuit, arranged to perform trimming control on the PLL, for supporting optimization of the PLL that uses the VCXO, wherein the optimization of the PLL comprises parameter adjustment of the PLL;
and
a register circuit, arranged to store multiple parameters of the PLL, and store multiple processing results of the parameter adjustment of the PLL, wherein the multiple parameters comprise multiple control parameters;
wherein:
the controller utilizes the processing circuit to set the multiple control parameters, for controlling the parameter adjustment of the PLL;
the controller utilizes the trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of the VCO, wherein the control voltage corresponds to the set of voltage parameters, and an oscillation frequency of the VCO corresponds to the control voltage;
and
during the parameter adjustment of the PLL, in response to at least one predetermined condition of the parameter adjustment of the PLL being satisfied, the controller utilizes the trimming control circuit to generate and store the multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving on-system PLL management of the memory device.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/161,552Filed 28 Jan 2021
Priority: 23 Jul 2020
Published: 27 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
H03L 7/235
With pulse counters or frequency dividers: nested phase locked loops
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 16/32
Auxiliary circuits, e.g. for writing into memory: timing circuits