System and method for stacking compression dual in-line memory module scalability

A method, comprising:

• affixing a first side of a first z-axis compression connector to a printed circuit board of an information handling system, the first compression connector having a first depth;
• affixing a first surface of a first memory circuit board of a first dual in-line memory module (DIMM) to a second side of the first compression connector;
• affixing a first side of a second z-axis compression connector to a second surface of the first memory circuit board, the second compression connector having a second depth that is different from the first depth;
• and
• affixing a first surface of a second memory circuit board of a second DIMM to a second side of the second compression connector.

An information handling system, comprising:

• a processor;
• a first z-axis compression connector having a first depth;
• a first dual in-line memory module (DIMM) including a plurality of first memory devices mounted on at least one of a first surface and second surface of a first memory circuit board of the first DIMM;
• a second z-axis compression connector having a second depth that is different from the first depth;
• a second DIMM including a plurality of second memory devices mounted on at least one of a first surface and second surface of a second memory circuit board of the second DIMM;
• and
• a printed circuit board, wherein a first side of the first compression connector is affixed to the printed circuit board, the first surface of the first memory circuit board is affixed to a second side of the compression connector, a first side of the second compression connector is affixed to the second side of the first memory circuit board, and the first side of the second memory circuit board is affixed to a second side of the second compression connector;
• wherein the processor accesses the first and second memory devices via one of at least two memory channels.