Vertical variable resistance memory devices

A vertical variable resistance memory device, comprising:

• gate electrode structures each including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes extending in a second direction, the gate electrode structures being spaced apart from each other in a third direction, the first direction being substantially perpendicular to an upper surface of the substrate, the second direction being substantially parallel to the upper surface of the substrate, the third direction being substantially parallel to the upper surface of the substrate and crossing the second direction, and the gate electrodes in each of the gate electrode structures being stacked in a staircase shape in which extension lengths of the gate electrodes in the second direction decrease in a stepwise manner from a lowermost level toward an uppermost level;
• first insulation patterns between the gate electrodes in each of the gate electrode structures, each of the first insulation patterns including hexagonal boron nitride (h-BN) or amorphous boron nitride (a-BN);
• second insulation patterns between the gate electrode structures, each of the second insulation patterns including h-BN or a-BN and electrically insulating the gate electrode structures from each other;
• and
• at least one pillar structure extending in the first direction on the substrate, the at least one pillar structure extending through the gate electrodes and the first insulation patterns therebetween in each of the gate electrode structures,
• wherein the at least one pillar structure includes:
• a vertical gate electrode extending in the first direction;
• and
• a variable resistance pattern on a sidewall of the vertical gate electrode, and wherein the second insulation pattern has an extension length in the second direction greater than or equal to an extension length of a lowermost one of the gate electrodes in each of the gate electrode structures.

A vertical variable resistance memory device, comprising:

• gate electrode structures each including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the gate electrode structures being spaced apart from each other in a third direction, the first direction being substantially perpendicular to an upper surface of the substrate, the second direction being substantially parallel to the upper surface of the substrate, and the third direction being substantially parallel to the upper surface of the substrate and crossing the second direction;
• first insulation patterns between the gate electrodes in each of the gate electrode structures, each of the first insulation patterns including hexagonal boron nitride (h-BN) or amorphous boron nitride (a-BN);
• second insulation patterns between the gate electrode structures, each of the second insulation patterns including h-BN or a-BN and electrically insulating the gate electrode structures from each other;
• pillar structures each extending in the first direction on the substrate, each of the pillar structures extending through the gate electrodes and the first insulation patterns therebetween in each of the gate electrode structures, and each of the pillar structures including:
• a vertical gate electrode including graphene and extending in the first direction;
• and
• a variable resistance pattern on a sidewall of the vertical gate electrode,
• first wirings each extending on the pillar structures in the third direction and electrically connected to the vertical electrodes of the pillar structures;
• and
• second wirings each extending in the second direction on the gate electrode structures and electrically connected to the gate electrode structures.