Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems

A method of forming an apparatus, the method comprising:

• removing portions of a channel material to form one or more channel regions separated by trenches;
• forming a liner material over bottom surfaces of the trenches and over sidewalls of the one or more channel regions;
• removing portions of the liner material from horizontal surfaces of the one or more channel regions;
• removing exposed portions of the channel material to form elongated trenches;
• removing portions of the channel material below the liner material without substantially removing the liner material to form upper regions of the channel regions and lower regions of the channel regions, each upper region defining at least one overhang portion extending outward beyond an outer boundary of a respective lower region;
• forming a gate dielectric material over the sidewalls of the lower regions and at least the at least one overhang portion of each of the upper regions of the channel regions;
• and
• forming gate electrodes adjacent to the gate dielectric material, at least a portion of each gate electrode being beneath a respective overhang portion of a respective upper region of the one or more channel regions.

An apparatus, comprising:

• at least one vertical transistor, comprising:
• a channel region:
• gate electrodes at least partially recessed within the channel region relative to an outermost surface of the channel region in a direction orthogonal to a longitudinal axis of the at least one vertical transistor;
• and
• a gate dielectric material between the gate electrodes and the channel region.

A memory array, comprising:

• memory cells, at least one memory cell of the memory cells comprising at least one vertical transistor, comprising:
• a channel region comprising:
• an upper region and a lower region, a width of the lower region being less than a width of the upper region;
• and
• gate electrodes laterally adjacent to the lower region of the channel region, at least a portion of the gate electrodes recessed below the upper region of the channel region;
• and
• a storage element in operative communication with the at least one vertical transistor.

A system, comprising:

• at least one input device;
• at least one output device;
• at least one processor device operably coupled to the at least one input device and the at least one output device;
• and
• an apparatus operably coupled to the at least one processor device, the apparatus comprising:
• an array of memory cells comprising vertical transistors, one or more of the vertical transistors comprising:
• a channel region comprising:
• an upper region exhibiting a first width;
• and
• a lower region extending downward from the upper region and exhibiting a second width, wherein the second width is smaller than the first width,
• wherein an interface between the upper region and the lower region defines at least one overhang portion;
• at least one gate electrode at least partially disposed vertically beneath the at least one overhang portion of the upper region of the channel region;
• and
• a gate dielectric material between the at least one gate electrode and the at least one overhang portion of the upper region and between the at least one gate electrode and the lower region of the channel region.