Semiconductor device with isolation layer

A semiconductor device, comprising:

• a base substrate;
• a first well region and a second well region in the base substrate, wherein a conductivity type of the first well region is opposite to a conductivity type of the second well region;
• a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate, wherein:
• the sidewall spacers cover sidewalls of the gate electrode structure;
• the doped source layer and the doped drain layer are respectively on two sides of the gate electrode structure and the sidewall spacers;
• the gate electrode structure and the sidewall spacers are on the first well region and the second well region;
• the doped source layer is in the first well region and the doped drain layer is in the second well region;
• and
• a conductivity type of the doped source layer and the doped drain layer is opposite to a conductivity type of the second well region;
• a dielectric layer on the base substrate, wherein the dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure;
• and
• an isolation layer in the dielectric layer, wherein the isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.