Vertically stacked field effect transistors
AssigneeGlobalFoundries U.S. Inc.
InventorsAnthony K. STAMPER, Steven M. SHANK, Siva P. ADUSUMILLI, Michel J. ABOU-KHALIL
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.
Claims20
A structure comprising:
- a single crystalline substrate material;
- a trench formed in the single crystalline substrate material;
- a first gate structure on a bottom of the trench, with source and drain regions formed in the single crystalline substrate material in the bottom of the trench;
- an epitaxial material of single crystalline material which is isolated from the single crystalline substrate material and the first gate structure;
- and
- a second gate structure on the epitaxial material of single crystalline material, with source and drain regions formed in the epitaxial material of single crystalline material.
A structure comprising:
- a substrate material;
- a trench in the substrate material;
- well implants provided at a bottom of the trench in the substrate material;
- a first gate structure on a bottom of the trench, with source and drain regions formed in the well implants in the bottom of the trench;
- a dielectric material which lines sidewalls of the trench;
- sidewall spacer material on the dielectric material and the first gate structure;
- insulator material over the sidewall spacer material;
- epitaxial semiconductor material over the insulator material;
- and
- a second gate structure on the epitaxial semiconductor material, with source and drain regions formed in the epitaxial semiconductor material.
A method comprising:
- forming a trench in the substrate material;
- forming well implants provided at a bottom of the trench in the substrate material;
- forming a first gate structure on a bottom of the trench, with source and drain regions formed in the well implants in the bottom of the trench;
- forming a dielectric material which lines sidewalls of the trench;
- forming sidewall spacer material on the dielectric material and the first gate structure;
- forming insulator material over the sidewall spacer material;
- forming epitaxial semiconductor material over the insulator material;
- and
- forming a second gate structure on the epitaxial semiconductor material, with source and drain regions formed in the epitaxial semiconductor material.
Dependencies are inferred from the claim text.