Scalable mps device based on sic

A method for manufacturing a Merged-PiN-Schottky (MPS) device, comprising:

• forming, on a substrate of silicon carbide having a first conductivity, a drift layer of silicon carbide having the first conductivity;
• forming a first junction-barrier, JB, diode with the substrate by forming, in the drift layer and at a first surface of the drift layer, a first implanted region having a second conductivity opposite to the first conductivity;
• and
• forming a first Schottky diode with the drift layer by forming a first electrical terminal in ohmic contact with a first surface of the first implanted region, coplanar with the first surface of the drift layer, and also in direct electrical contact with the first surface of the drift layer laterally to the first implanted region,
• the first JB diode and the first Schottky diode being alternated to each other, at the first electrical terminal, along a first axis so that the first JB diode has, at the first surface of the first implanted region, a first width which is parallel to the first axis, and the first Schottky diode has, at the first surface of the drift layer, a second width which is parallel to the first axis, the second width is smaller than, or equal to, the first width, and
• the drift layer having an dopant concentration such that a breakdown voltage of the MPS device, beyond which a charge carrier multiplication phenomenon occurs, is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

A device, comprising:

• a substrate of a first conductivity type;
• a drift layer of the first conductivity type, the drift layer having a first surface;
• a first implanted region of a second conductivity type extending into the drift layer from the first surface, the first implanted region having a first dimension in a first direction;
• a second implanted region of the second conductivity type extending into the drift layer from the first surface, the second implanted region having a second dimension in the first direction, the second implanted region being spaced from the first implanted region by a third dimension in the first direction, the third dimension being less than the second dimension, the third dimension being less than the first dimension;
• a first terminal on the first surface of the drift layer, the first terminal being on the first and second implanted regions, the first terminal having a fourth dimension in the first direction, the fourth dimension being greater than a sum of the first, second, and third dimensions;
• a first Schottky diode between the first terminal and the drift layer between the first and second implanted regions;
• a first junction barrier diode between the first implanted region and the first terminal;
• and
• a second junction barrier diode between the second implanted region and the first terminal.