US 2022/0028972 A1 · TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN

Abstract

A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Claims20

Dependent claims

An integrated circuit comprising:

a body of semiconductor material, the body having a bottommost surface;
a gate structure in contact with a portion of the body, the gate structure defining a channel region in the body;
a source region in contact with the body;
drain region in contact with the body such that the portion of the body in contact with the gate structure is between the source region and the drain region;
a first isolation region under the source region and having a top surface in contact with a portion of a bottom surface of the source region laterally adjacent to the channel region, the first isolation region having an uppermost surface above the bottommost surface of the body;
and
a second isolation region under the drain region and having a top surface in contact with a portion of a bottom surface of the drain region laterally adjacent to the channel region, the second isolation region having an uppermost surface above the bottommost surface of the body.

4 more elements

An integrated circuit comprising:

a semiconductor fin comprising
an upper fin portion of a first semiconductor material, the upper fin portion having a body portion, a source region extending laterally from a first side of the body portion, and a drain region extending laterally from a second side of the body portion, with the body portion between the source region and the drain region, the body portion having a bottommost surface, and
a lower fin portion of a second semiconductor material, the lower fin portion having a fin stub with laterally opposed sidewalls extending upwardly towards the upper fin portion;
a gate structure in direct contact with the body portion, the gate structure defining a channel region in the body portion;
a first insulator structure below the source region and having a first insulator top surface in contact with a portion of a bottom surface of the source region laterally adjacent to the channel region, the first insulator structure having an uppermost surface above the bottommost surface of the body portion;
and
a second insulator structure below the drain region and having a second insulator top surface in contact with a portion of a bottom surface of the drain region laterally adjacent to the channel region, the second insulator structure having an uppermost surface above the bottommost surface of the body portion;
wherein the fin stub is between the first insulator and the second insulator with a first one of the laterally opposed sidewalls in contact with a sidewall of the first insulator structure and a second one of the laterally opposed sidewalls in contact with an entirety of a portion of a bottom surface of the drain region laterally adjacent to the channel region.

5 more elements

Dependencies are inferred from the claim text.

Transistor with isolation below source and drain

Life of this patent

Transistor with isolation below source and drain

Life of this patent

Abstract

Claims20