Magnetic memory device

A magnetic memory device comprising:

• a plurality of first active regions spaced apart from one another in a first direction and a second direction in a first region, the first and second directions being perpendicular to each other;
• a plurality of second active regions spaced apart from one another in the first direction and extending in the second direction in a second region;
• a plurality of first bit lines in the first region and a plurality of second bit lines in the second region;
• a plurality of first source lines respectively corresponding to the plurality of first bit lines and a plurality of second source lines respectively corresponding to the plurality of second bit lines;
• a plurality of first memory cells connected between the plurality of first bit lines and the plurality of first source lines, respectively, in the first region, the plurality of first memory cells each comprising a first memory device and a first selection transistor;
• and
• a plurality of second memory cells connected between the plurality of second bit lines and the plurality of second source lines, respectively, in the second region, the plurality of second memory cells each comprising a second memory device and a second selection transistor,
• wherein the plurality of first source lines extend in the second direction,
• the plurality of second source lines extend in the first direction, and
• one or more of the second memory devices are configured to be programmed to an irreversible resistance state.

A magnetic memory device comprising:

• a memory cell array comprising a normal cell array and a one time programmable (OTP) cell array;
• and
• a peripheral circuit electrically connected to the normal cell array and the OTP cell array, wherein
• the normal cell array comprises a plurality of first memory cells each comprising a first magnetic tunnel junction (MTJ) and a first selection transistor,
• the OTP cell array comprises a plurality of second memory cells each comprising a second MTJ and a second selection transistor,
• one or more of the second MTJs are configured to be programmed to an irreversible resistance state, and
• a first active region occupied by the plurality of first memory cells is smaller than a second active region occupied by the plurality of second memory cells.