Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors

An array of vertical transistors, comprising:

• spaced pillars of individual vertical transistors;
• the spaced pillars individually comprising an upper source/drain region, a lower source/drain region, and a channel region vertically there-between;
• the upper source/drain region comprising a conductor oxide material in individual of the pillars, the channel region comprising an oxide semiconductor material in the individual pillars, the lower source/drain region comprising a first conductive oxide material in the individual pillars;
• horizontally-elongated and spaced conductor lines that individually interconnect a respective multiple of the vertical transistors in a column direction, the conductor lines individually comprising a second conductive oxide material atop and directly against metal material;
• the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative one another;
• the second conductive oxide material of the conductor lines being below and directly against the first conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors;
• horizontally-elongated and spaced conductive gate lines individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and that individually interconnect a respective plurality of the vertical transistors in a row direction;
• and
• a conductive structure laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction, the conductive structures individually comprising a top surface that is higher than a top surface of the metal material of the conductor lines.

An array of vertical transistors, comprising:

• spaced pillars of individual vertical transistors;
• the spaced pillars individually comprising an upper source/drain region above a channel region, the upper source/drain region comprising a conductor oxide material in individual of the pillars, the channel region comprising an oxide semiconductor material in the individual pillars;
• horizontally-elongated and spaced conductor lines that individually interconnect a respective multiple of the vertical transistors in a column direction;
• the conductor lines individually comprising a first conductive oxide material, a second conductive oxide material, and a metal material;
• the first conductive oxide material, the second conductive oxide material, and the metal material comprising different compositions relative one another;
• the first conductive oxide material in the conductor lines being atop and directly against the second conductive oxide material in the conductor lines, the second conductive oxide material in the conductor lines being atop and directly against the metal material in the conductor lines, the first conductive oxide material of the conductor lines being below and directly against the oxide semiconductor material of the channel regions of the individual pillars of the respective multiple vertical transistors;
• horizontally-elongated and spaced conductive gate lines individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and that individually interconnect a respective plurality of the vertical transistors in a row direction;
• and
• a conductive structure laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction, the conductive structures individually comprising a top surface that is higher than a top surface of the metal material of the conductor lines.

A method used in forming an array of vertical transistors, comprising:

• forming laterally-spaced and horizontally-elongated line constructions in a column direction;
• the line constructions comprising insulator material, metal material above the insulator material, transistor material above the metal material, and insulating material on lateral sides of the insulator material, the metal material, and the transistor material;
• the transistor material comprising an upper source/drain region above a channel region of what will be individual vertical transistors, the insulator material of the line constructions being above conductive material;
• forming a horizontally-elongated conductive line in the column direction between immediately-laterally-adjacent of the line constructions and directly against the conductive material, the conductive lines individually comprising a top surface that is higher than a top surface of the metal material and at or below a bottom of the channel region;
• after forming the conductive lines, cutting the transistor material to form spaced pillars individually comprising the upper source/drain region and the channel region of the individual vertical transistors;
• and
• forming a horizontally-elongated conductive gate line operatively aside the channel region of individual of the pillars that interconnects a respective plurality of the vertical transistors in a row direction.