Method of manufacturing an integrated circuit device

A method of manufacturing an integrated circuit device, the method comprising:

• preparing a semiconductor-on-insulator (SOI) substrate, on which a base substrate layer, an embedded insulation layer, and a semiconductor layer are sequentially stacked;
• forming a deep trench that defines at least two element regions, by partially removing the semiconductor layer;
• forming a preliminary separation insulation layer to fill the deep trench;
• forming a buried rail hole that penetrates through the preliminary separation insulation layer and the semiconductor layer, a buried rail partially filled in a lower portion of the buried rail hole, and a preliminary cover insulation layer filled in an upper portion of the buried rail hole;
• exposing the embedded insulation layer by removing the base substrate layer;
• and
• forming a power delivery structure in the embedded insulation layer, the power delivery structure being in contact with the buried rail.

A method of manufacturing an integrated circuit device, the method comprising:

• preparing a semiconductor-on-insulator (SOI) substrate, on which a base substrate layer, an embedded insulation layer, and a semiconductor layer are sequentially stacked;
• forming a plurality of preliminary fin-type active areas by partially etching the semiconductor layer, and a preliminary isolation layer covering the plurality of preliminary fin-type active areas on the semiconductor layer, the plurality of preliminary fin-type active areas protruding perpendicularly from a main surface of the semiconductor layer and extending in a first horizontal direction;
• forming a deep trench by partially removing the preliminary isolation layer and the semiconductor layer, the deep trench defining a plurality of element regions, and forming a preliminary separation insulation layer that is filled in the deep trench;
• forming a buried rail hole that penetrates through the preliminary separation insulation layer and the semiconductor layer, a buried rail partially filled in a lower portion of the buried rail hole, and a preliminary cover insulation layer filled in an upper portion of the buried rail hole;
• exposing the embedded insulation layer by removing the base substrate layer;
• forming a power delivery hole by partially removing the embedded insulation layer, wherein the embedded insulation layer is partially removed by using a mask pattern as an etching mask, wherein the mask pattern is obtained by a photolithography process in which the buried rail functions as an alignment key;
• and
• forming a power delivery structure that is filled in the power delivery hole, the power delivery structure being in contact with the buried rail to be electrically connected to the buried rail.