Nand flash memory and manufacturing method thereof
AssigneeWinbond Electronics Corp.
InventorRiichiro Shirota
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Abstract
A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.
Claims15
A three-dimensional NAND flash memory, comprising:
- a substrate;
- a lower conductive layer formed in or on the substrate;
- a plurality of stacks extending along a first direction on the lower conductive layer and respectively comprising stacks of insulators and conductors stacked along a vertical direction from the substrate;
- a plurality of channel stacks separately arranged along one side of the plurality of stacks and respectively comprising an insulating layer comprising a charge storage layer and a channel film, the insulating layer and the channel film extending along a vertical direction from the substrate, and a lower end of the channel film being electrically connected to the lower conductive layer;
- and
- a plurality of upper conductive layers extending along a second direction orthogonal to the first direction, respectively arranged on the plurality of channel stacks, and electrically connected to an upper end of the crossed channel film.
A manufacturing method of a flash memory, applicable to a three-dimensional NAND flash memory, comprising:
- a step of forming a lower conductive layer in or on a substrate;
- a step of forming a stack by alternately stacking insulators and conductors on the lower conductive layer;
- a step of etching the stack at a depth reaching the lower conductive layer to form a plurality of stacks extending along a first direction;
- a step of forming channel stacks on an entire surface of the substrate comprising the plurality of stacks;
- a step of etching the channel stacks to separately arrange the channel stacks along one side of each of the plurality of stacks;
- a step of forming a plurality of upper conductive layers extending along a second direction orthogonal to the first direction on the channel stacks;
- and
- a step of electrically connecting the plurality of upper conductive layers to an upper end of the crossed channel stack, respectively.
Dependencies are inferred from the claim text.