Integrated circuit devices with highly integrated memory and peripheral circuits therein

An integrated circuit device, comprising:

• a plurality of circuit patterns on a substrate;
• a lower insulating interlayer on the circuit patterns;
• base semiconductor patterns on the lower insulating interlayer, said base semiconductor patterns including first and second base semiconductor patterns, which are spaced apart from each other by an opening extending therebetween;
• a memory cell stack structure on the base semiconductor patterns;
• a channel structure in a channel hole that passes through the memory cell stack structure, said channel structure including a channel electrically connected to an underlying one of the base semiconductor patterns;
• a dummy mold structure on the base semiconductor patterns and the first opening, the dummy mold structure being spaced apart from the cell stack structure;
• and
• a lower insulation pattern, which fills a space between the memory cell stack structure and the dummy mold structure, said lower insulation pattern having an upper surface that is substantially coplanar with an upper surface of the memory cell stack structure and an upper surface of the dummy mold structure;
• and
• wherein the dummy mold structure comprises:
• a first dummy mold structure including first insulation layers and first sacrificial layers, which are alternately stacked, have upper and lower surfaces that are not planar, and include center portions with dish-shaped cross sections;
• a first lower insulation pattern, which fills a dish-shaped recess in an upper surface of the first dummy mold structure;
• and
• an upper dummy mold structure on the first dummy mold structure and the first lower insulation pattern, the upper dummy mold structure including second insulation layers and second sacrificial layers, which are alternately stacked and have substantially planar upper and lower surfaces.

An integrated circuit device, comprising:

• a plurality of circuit patterns on a substrate;
• a lower insulating interlayer on the circuit patterns;
• a vertical stack of nonvolatile memory cells on a first portion of the lower insulating interlayer, said vertical stack of nonvolatile memory cells including a plurality of electrically insulating layers and a plurality of gate patterns arranged as an alternating stack of electrically insulating layers and gate patterns;
• a dummy mold structure on a second portion of the lower insulating interlayer, said dummy mold structure including:
• a first alternating stack of first electrically insulating layers and first sacrificial layers having respective dish-shaped cross sections, and a second alternating stack of second electrically insulating layers and second sacrificial layers having substantially planar upper and lower surfaces thereon;
• and
• an insulation pattern, which:
• (i) fills a dish-shaped recess in the first alternating stack of first electrically insulating layers and first sacrificial layers, (ii) has a substantially planar upper surface, and (iii) extends between an uppermost surface of the first alternating stack of first electrically insulating layers and first sacrificial layers and a lowermost surface of the second alternating stack of second electrically insulating layers and second sacrificial layers.