Methods for fabricating a 3-dimensional memory structure of nor memory strings

A process, comprising:

• providing over a planar surface of a semiconductor substrate a semiconductor structure which comprises a plurality of active multi-layers which are stacked one on top of another along a first direction that is substantially normal to the planar surface, wherein adjacent active multi-layers are electrically isolated from each other by a layer of dielectric material, and wherein each active multi-layer comprises first and second semiconductor layers of a first conductivity type separated by a dielectric material;
• providing a plurality of shafts arrayed in a regular pattern along both a second direction and a third direction, the second and third directions being substantially orthogonal to each other and each being orthogonal to the first direction, each shaft extending in depth along the first direction through the semiconductor structure and having a predetermined extent along the second direction;
• providing a plurality of trenches in the semiconductor structure each extending in depth along the first direction and in length along the third direction, each trench (a) intersecting a plurality of the shafts in the second direction, and (b) having a width along the second direction that is less than the extent of each shaft;
• and
• forming, in either (i) each shaft, or (ii) portions of each trench between adjacent shafts:
• (a) a third semiconductor layer of a second conductivity type opposite the first conductivity type, the third semiconductor layer being formed adjacent to and in contact with the first and second semiconductor layers of each active multi-layer, (b) a charge-trapping layer adjacent the third semiconductor layer;
• and (c) a conductor layer in contact with the charge-trapping layer.