Pillar-shaped semiconductor device and manufacturing method thereof

A manufacturing method of a pillar-shaped semiconductor device, in forming a SRAM (Static Random Access Memory) circuit configuring one cell area by six or eight SGTs (Surrounding Gate Transistor) on a substrate, the method comprising steps of:

• forming a first material layer over a semiconductor layer;
• forming four or five band-like first mask material layers which are parallel to and separated from each other in a first direction in planar view over the first material layer in the cell area;
• with two band-like second mask material layers, which are parallel to and separated from each other in a direction orthogonal to the first direction in planar view, being formed in the cell area located below or above the band-like first mask material layers,
• forming a third mask material layer consisting of a part or all of the first material layer, the band-like first mask material layer, and the band-like second mask material layer on a part where the band-like first mask material layer and the band-like second mask material layer are overlapped;
• etching the semiconductor layer with the third mask material layer as a mask to form a first set of semiconductor pillars aligned on a first line, and a second set of semiconductor pillars aligned on a second line parallel to the first line;
• wherein arrangement is made such that:
• a first semiconductor pillar is present on one end on the first line in the first set of semiconductor pillars, a second semiconductor pillar is present on an end opposite to the one end on the second line in the second set of semiconductor pillars, and a third semiconductor pillar is present as having a center at a point where a first center line extending through a center of the first semiconductor pillar, orthogonal to the first line and the second line cross;
• and
• a fourth semiconductor pillar is present as having a center at a point where a second center line extending through a center of the second semiconductor pillar, orthogonal to the second line and the first line cross, a fifth semiconductor pillar is present as having a center on the first line and being adjacent to the fourth semiconductor pillar, and a sixth semiconductor pillar is present as having a center on the second line and being adjacent to the third semiconductor pillar;
• wherein arrangement is made such that, in planar view, a first semiconductor pillar-absent area having no semiconductor pillar of the first set of semiconductor pillars is present in, at least a part being overlapped on, a first band area, the first band area being an extension of insides of two tangential lines of periphery of the sixth semiconductor pillar, the two tangential lines being parallel to the first center line, and a second semiconductor pillar-absent area having no semiconductor pillar of the second set of semiconductor pillars is present in, at least a part being overlapped on, a second band area, the second band area being an extension of insides of two tangential lines of periphery of the fifth semiconductor pillar, the two tangential lines being parallel to the second center line;
• forming a gate insulating layer surrounding the first set of semiconductor pillars and the second set of semiconductor pillars;
• forming a first gate conductor layer surrounding the gate insulating layer of the third semiconductor pillar and the sixth semiconductor pillar, and being linked, a second gate conductor layer surrounding the gate insulating layer of the fourth semiconductor pillar and the fifth semiconductor pillar, and being linked, a third gate conductor layer surrounding the gate insulating layer of the first semiconductor pillar, and a fourth gate conductor layer surrounding the gate insulating layer of the second semiconductor pillar;
• and
• forming a first contact hole connecting a first impurity area formed as being linked to a bottom of the first set of semiconductor pillars and the first gate conductor layer on the first semiconductor pillar-absent area, and forming a second contact hole connecting a second impurity area formed as being linked to a bottom of the second set of semiconductor pillars and the second gate conductor layer on the second semiconductor pillar-absent area;
• wherein the first gate conductor layer is formed such that it contacts at entire side surface of a first channel region of the third semiconductor pillar and the sixth semiconductor pillar in a vertical direction, and the second gate conductor layer is formed such that it contacts at entire side surface of a second channel region of the fourth semiconductor pillar and the fifth semiconductor pillar in a vertical direction.