Semiconductor memory devices and methods of fabricating the same

A semiconductor memory device comprising:

• a substrate having a first active pattern, a second active pattern, and a third active pattern that are sequentially arranged in a first direction;
• a bit line crossing the second active pattern and extending in a second direction, the bit line being electrically connected to the second active pattern;
• a first contact coupled to the first active pattern;
• a second contact coupled to the third active pattern;
• landing pads on the first and second contacts, respectively;
• and
• data storing elements on the landing pads, respectively,
• wherein the first contact is in contact with a curved top surface of the first active pattern,
• wherein the second contact is in contact with a curved top surface of the third active pattern,
• wherein a lowermost level of the curved top surface of the first active pattern is at a first level,
• wherein a lowermost level of the curved top surface of the third active pattern is at a second level,
• wherein a lowermost level of the first contact is at a third level,
• wherein a lowermost level of the second contact is at a fourth level, and
• wherein a difference between the first level and the second level is larger than a difference between the third level and the fourth level.

A semiconductor memory device comprising:

• a substrate including an active pattern, the active pattern having a longitudinal axis parallel to a first direction and comprising a first source/drain region and a pair of second source/drain regions that are spaced apart from each other in the first direction with the first source/drain region interposed therebetween;
• a device isolation layer on the substrate, in a first trench defining the active pattern;
• a pair of gate electrodes crossing the active pattern and extending in a second direction, each of the pair of gate electrodes being in a second trench between the first source/drain region and a first one of the pair of second source/drain regions;
• a gate dielectric layer interposed between each of the pair of gate electrodes and the active pattern;
• a gate capping layer on each of the pair of gate electrodes, in the second trench;
• an insulating layer on the substrate;
• a line structure on the insulating layer to cross the active pattern and extend in a third direction, the line structure comprising:
• a conductive pattern that penetrates the insulating layer and is coupled to the first source/drain region;
• a bit line on the conductive pattern;
• and
• a barrier pattern between the bit line and the conductive pattern;
• a pair of spacers on opposite side surfaces of the line structure, respectively;
• a first contact and a second contact that are in contact with the first one and a second one of the pair of second source/drain regions, respectively, the first and second contacts being spaced apart from the line structure by the pair of spacers;
• landing pads on the first and second contacts, respectively;
• first electrodes on the landing pads, respectively;
• a second electrode on the first electrodes;
• and
• a dielectric layer interposed between the first electrodes and the second electrode,
• wherein a bottom surface of the conductive pattern in contact with the first source/drain region is at a level higher than a lowermost level of the first contact.