Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJaeho HONG, Kyunghwan Lee, Hyuncheol Kim, Huijung Kim, Hyunmog Park, Kiseok Lee, Minhee Cho
Life of this patent
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Abstract
A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.
Claims22
A memory device comprising:
- a substrate;
- a memory unit provided on the substrate;
- a channel provided on the memory unit;
- a word line surrounded by the channel and extending in a first horizontal direction;
- a gate insulating layer interposed between the channel and the word line;
- and
- a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.
(canceled)
A memory device comprising:
- a substrate;
- a lower electrode provided on the substrate;
- an upper electrode provided on the lower electrode;
- a dielectric layer provided between the lower electrode and the upper electrode;
- a memory unit contact provided on the upper electrode;
- a channel comprising a first portion and a second portion, each of the first portion and the second portion extending from the memory unit contact in a vertical direction perpendicular to a first horizontal direction;
- a word line extending in the first horizontal direction and passing between the first portion and the second portion of the channel;
- a gate insulating layer interposed between the channel and the word line;
- and
- a bit line contacting upper ends of the first portion and the second portion of the channel and extending in a second horizontal direction perpendicular to the vertical direction.
A memory device comprising:
- a substrate;
- a lower electrode provided on the substrate;
- a dielectric layer provided on the lower electrode;
- a plurality of upper electrodes provided on the dielectric layer;
- a plurality of channels respectively provided on the plurality of upper electrodes and extending in a vertical direction;
- a plurality of word lines respectively provided on sides of the plurality of channels and extending in a first horizontal direction perpendicular to the vertical direction;
- a plurality of gate insulating layers respectively interposed between the plurality of channels and the plurality of word lines;
- and
- a bit line contacting upper ends of the plurality of channels and extending in a second horizontal direction that crosses the first horizontal direction and is perpendicular to the vertical direction.
22-36. (canceled)
Dependencies are inferred from the claim text.