Memory device including double pn junctions and driving method thereof, and capacitor-less memory device including double pn junctions and control gates and operation method thereof

An operation method of a memory device including a double PN junction, comprising:

• applying a program voltage to the memory device;
• lowering resistance of at least one semiconductor layer by lowering a potential barrier of the double PN junction by the program voltage to move carriers to the semiconductor layer;
• and
• reading the resistance of the semiconductor layer,
• wherein the memory device comprises:
• the semiconductor layer having the double PN junction;
• and
• an anode and a cathode which simultaneously contact the semiconductor layer, and
• wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction.

A capacitor-less memory device including a double PN junction and a control gate, comprising:

• at least one semiconductor layer having a double PN junction;
• a control gate which contacts the semiconductor layer;
• and
• an anode and a cathode which simultaneously contact the semiconductor layer,
• wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction.