Integrated circuit (ic) device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyun-jo KIM, Joong-won JEON
Life of this patent
Estimating the term…
Abstract
Provided is an integrated circuit (IC) device including a logic cell having an area defined by a cell boundary. The logic cell includes a first device region, a device isolation region, and a second device region. The first device region and the second device region are arranged apart from each other in a first direction that is perpendicular to a second direction. The device isolation region is between the first device region and the second device region. A first maximum length of the first device region in the second direction is less than a width of the cell boundary in the second direction, and a second maximum length of the second device region is substantially equal to the width of the cell boundary in the second direction.
Claims20
An integrated circuit (IC) device comprising:
- a first logic cell and a second logic cell adjacent to each other in a width direction, each of the first logic cell and the second logic cell including a first device region and a second device region spaced apart from each other in a height direction perpendicular to the width direction, and the first device region and the second device region having different lengths in the width direction;
- a plurality of first, fin-type active regions extending in the width direction on the first device region in each of the first logic cell and the second logic cell;
- a plurality of second fin-type active regions extending in the width direction on the second device region in each of the first logic cell and the second logic cell;
- and
- a fin separation insulating portion between the first logic cell and the second logic cell and adjacent to the second device region of each of the first logic cell and the second logic cell,
- the fin separation insulating portion extending along a cell boundary of each of the first logic cell and the second logic cell.
An integrated circuit (IC) device comprising:
- a first logic cell and a second logic cell adjacent to each other in a width direction, each of the first logic cell and the second logic cell including a first device region and a second device region spaced apart from each other in a height direction perpendicular to the width direction;
- a plurality of first fin-type active regions extending in the width direction on the first device region in each of the first logic cell and the second logic cell;
- a plurality of second fin-type active regions extending in the width direction on the second device region in each of the first logic cell and the second logic cell;
- a plurality of gate structures extending in the height direction over the first device region and the second device region in each of the first logic cell and the second logic cell;
- a first fin separation insulating portion between the first device region of the first logic cell and the first device region of the second logic cell;
- and
- a second fin separation insulating portion (FS2) vertically overlying the second device region of each of the first logic cell and the second logic cell,
- the second fin separation insulating portion extending along a cell boundary of each of the first logic cell and the second logic cell.
An integrated circuit (IC) device comprising:
- a substrate;
- a first logic cell and a second logic cell that are adjacent to each other in a width direction on the substrate, each of the first logic cell and the second logic cell including a first device region and a second device region spaced apart from each other in a height direction perpendicular to the width direction, and each of the first device region and the second device region being defined by a trench in the substrate that extends in the width direction between the first device region and the second device region;
- a fin separation insulating portion vertically overlying the second device region of each of the first logic cell and the second logic cell;
- and
- a gate structure extending in the height direction along a cell boundary contact portion where a first cell boundary of the first logic cell and a second cell boundary of the second logic cell meet each other,
- the gate structure and the fin separation insulating portion being aligned with the cell boundary contact portion, and
- the first logic cell and the second logic cell being asymmetrical about the cell boundary contact portion.
Dependencies are inferred from the claim text.