Semiconductor package including interposer
AssigneeSamsung Electronics Co., Ltd.
InventorKIWON BAEK
Life of this patent
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Abstract
A semiconductor package includes a processor, a lower memory including a plurality of lower memory chips that are vertically stacked, an interposer mounted on the processor and the lower memory, and an upper memory mounted on the interposer, the upper memory including a plurality of upper memory chips that are vertically stacked. The interposer includes a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory, and the processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.
Claims21
A semiconductor package, comprising:
- a processor;
- a first memory including a plurality of first memory chips;
- an interposer disposed over the processor and the first memory;
- and
- a second memory disposed over the interposer, the second memory including a plurality of second memory chips,
- wherein the interposer is disposed between the first memory and the second memory,
- wherein the interposer comprises a first physical layer (PHY) transmitting and receiving a signal between the processor and the first memory and transmitting and receiving a signal between the processor and the second memory,
- wherein the processor comprises a second PHY communicating with the first PHY, and
- wherein a first through silicon via (TSV) electrically connects the first PHY to the second PHY.
A semiconductor package, comprising:
- a processor disposed on a substrate;
- a lower memory including a plurality of lower memory chips;
- an upper memory including a plurality of upper memory chips which are vertically stacked;
- and
- an interposer disposed between the lower memory and the upper memory,
- wherein the interposer comprises:
- a first physical layer (PHY) transmitting and receiving a signal between the processor and the lower memory and transmitting and receiving a signal between the processor and the upper memory;
- a power through silicon via (TSV) passing through the interposer, receiving a power signal from the lower memory, and transferring the power signal to the upper memory;
- and
- a data TSV passing through the interposer, receiving a data signal from the lower memory or the upper memory, and transferring the data signal to the first PHY,
- wherein the processor comprises:
- a second PHY communicating with the first PHY;
- and
- a TSV electrically connecting the first PHY to the second PHY, and
- the first PHY vertically overlaps the second PHY.
A semiconductor package, comprising:
- a processor disposed on a substrate;
- a lower memory including a plurality of lower memory chips vertically stacked on the substrate;
- an interposer disposed on the processor and the lower memory;
- and
- a first upper memory disposed on the interposer, the first upper memory including a plurality of upper memory chips that are vertically stacked,
- wherein the interposer comprises:
- a first physical layer (PHY) electrically connected to the processor, the first upper memory, and the lower memory;
- a redistribution layer electrically connecting the lower memory to the first PHY and electrically connecting the first upper memory to the first PHY;
- and
- a power through silicon via (TSV) passing through the interposer, receiving a power signal from the lower memory, and transferring the power signal to the first upper memory,
- wherein the processor comprises:
- a second PHY communicating with the first PHY;
- a first TSV electrically connecting the first PHY to the second PHY;
- and
- a second TSV receiving a power signal from the substrate and transferring the power signal to the power TSV, and
- wherein the first PHY at least partially vertically overlaps the second PHY.
21-26. (canceled)
Dependencies are inferred from the claim text.