Semiconductor package including stacked semiconductor chips

The semiconductor package according to claim wherein the chip pads are disposed along first and second side edges of the sub semiconductor chip in a first direction and along third and fourth side edges of the sub semiconductor chip in a second direction, the second direction being perpendicular to the first direction,

• wherein the signal redistribution pad includes a plurality of signal redistribution pads that are disposed at first and second side edges of the sub molding layer in the first direction,
• wherein the signal redistribution conductive layer includes a plurality of signal redistribution conductive layers,
• wherein the signal redistribution conductive layers, connected to the chip pads that are disposed at the first side edge and the third side edge of the sub semiconductor chip, extend toward the signal redistribution pads that are disposed at the first side edge of the sub molding layer, and
• wherein the signal redistribution conductive layers, connected to the chip pads that are disposed at the second side edge and the fourth side edge of the sub semiconductor chip, extend toward the signal redistribution pads that are disposed at the second side edge of the sub molding layer.

The semiconductor package according to claim wherein the substrate includes substrate pads that are disposed at a first side edge and a second side edge of the substrate in a first direction, and

• wherein the main semiconductor chip includes:
• at least one first rnain semiconductor chip connected to the substrate pads that are disposed at the first side edge of the substrate through a first main interconnector;
• and
• at least one second main semiconductor chip connected to the substrate pads that are disposed at the second side edge of the substrate through a second main interconnector.

The semiconductor package according to claim 12, further comprising:

• a main interconnector that connects the main semiconductor chip to the substrate,
• wherein the signal sub interconnector includes an internal signal sub interconnector that exchanges a signal between the main semiconductor chip and the sub semiconductor chip, wherein the main interconnector includes a signal main interconnector that exchanges the signal between the main semiconductor chip and the sub semiconductor chip,
• wherein the substrate includes an internal signal sub substrate pad that is connected to the internal signal sub interconnector, and a signal main substrate pad that is connected to the signal main interconnector, and
• wherein the internal signal sub substrate pad and the signal main substrate pad are connected to each other by a connection line that is formed in the substrate.

The semiconductor package according to claim 12, wherein the chip pads are disposed along first and second side edges of the sub semiconductor chip in a first direction and along third and fourth side edges of the sub semiconductor chip in a second direction, the second direction being perpendicular to the first direction,

• wherein the signal redistribution conductive layer includes a plurality of signal redistribution conductive layers with a plurality of signal redistribution pads formed at their end portions,
• wherein the power redistribution conductive layer includes a plurality of power redistribution conductive layers with a plurality of second power redistribution pads formed at their end portions,
• wherein the signal redistribution pads and the second power redistribution pads are disposed at first and second side edges of the sub molding layer in the first direction,
• wherein the signal redistribution conductive layers and the power redistribution conductive layers, connected to the chip pads that are disposed at the first side edge and the third side edge of the sub semiconductor chip, extend toward the signal redistribution pads and the second power redistribution pads that are disposed at the first side edge of the sub molding layer, and
• wherein the signal redistribution conductive layers and the power redistribution conductive layers, connected to the chip pads that are disposed at the second side edge and the fourth side edge of the sub semiconductor chip, extend toward the signal redistribution pads and the second power redistribution pads that are disposed at the second side edge of the sub molding layer.

The semiconductor package according to claim 12, wherein the substrate includes substrate pads disposed at a first side edge and a second side edge of the substrate in a first direction, and

• wherein the main semiconductor chip includes:
• at least one first main semiconductor chip connected to the substrate pads that are disposed at the first side edge of the substrate through a first main interconnector;
• and
• at least one second main semiconductor chip connected to the substrate pads that are disposed at the second side edge of the substrate through a second main interconnector.

A semiconductor package, comprising:

• a substrate;
• a sub semiconductor package with a sub semiconductor chip disposed over the substrate, the sub semiconductor package further comprising:
• chip pads positioned on a surface of the sub semiconductor chip that faces the substrate;
• a sub molding layer surrounding side surfaces of the sub semiconductor chip in such a way that the sub molding layer has a surface that faces the substrate, wherein the surface of the sub molding layer is on a same level as the surface of the sub semiconductor chip that faces the substrate;
• and
• redistribution conductive layers that connect to the chip pads, wherein the redistribution conductive layers include a signal redistribution conductive layer and a power redistribution conductive layer, wherein the signal redistribution conductive layer has a signal redistribution pad on its end portion and the power redistribution conductive layer has a power redistribution pad on its end portion, and wherein a length of the power redistribution conductive layer is shorter than a length of the signal redistribution conductive layer;
• a signal sub interconnector with an upper surface that is connected to the signal redistribution pad and a lower surface that is connected to the substrate;
• a power sub interconnector with an upper surface that is connected to the power redistribution pad and a lower surface that is connected to the substrate;
• and
• at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate,