Multi-chip package structure

A multi-chip package structure, comprising:

• a package carrier comprising a chip bonding area disposed on a central part thereof, and a plurality of outer leads disposed on at least one side thereof and configured to be electrically connected to an external preset electronic circuit;
• and
• at least two chips comprising a first chip and a second chip, wherein the first chip is fixed on the chip bonding area of the package carrier and comprises an core disposed therein, and a plurality of input/output units and a plurality of first bonding pads disposed in an outward order from at least one side of the core and electrically connected to the core, and each of the plurality of first bonding pads is electrically connected to the corresponding one of the plurality of outer leads through a first wire, and the first chip further comprises a plurality of dummy pads disposed thereon, and each of the plurality of dummy pads is disposed between one of the plurality of input/output units and the at least one side of the core;
• wherein the second chip is stacked and fixed on a top of the core of the first chip, and comprises at least one group of second bonding pads electrically connected to the corresponding ones of the plurality of outer leads through a plurality of second wires and the plurality of dummy pads.