Semiconductor devices and methods for manufacturing the same

A semiconductor device, comprising:

• an interposer substrate;
• and
• at least one die mounted on the interposer substrate,
• wherein the interposer substrate includes
• a semiconductor substrate having a first surface and a second surface opposite to the first surface, the semiconductor substrate including a capacitor region, a first connection region, a second connection region, and a through-via region,
• an interlayer insulating layer on the first surface of the semiconductor substrate,
• a capacitor in the interlayer insulating layer on the capacitor region,
• an interconnection layer on the interlayer insulating layer, and
• a through-via at least partially in the through-via region and extending from the interconnection layer toward the second surface of the semiconductor substrate in a vertical direction that is perpendicular to the first surface of the semiconductor substrate,
• wherein the capacitor includes a sequential stack of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode,
• wherein the first connection region and the second connection region are both located between the capacitor region and the through-via region in a horizontal direction that is parallel to the first surface of the semiconductor substrate, and the second connection region is located between the capacitor region and the first connection region in the horizontal direction,
• wherein the first electrode extends from the capacitor region onto the first connection region, and the first electrode has an opening on the second connection region,
• wherein the second electrode extends from the capacitor region onto the second connection region, and the second electrode on the second connection region vertically overlaps with the opening.

A semiconductor device, comprising:

• a package substrate;
• an interposer substrate on the package substrate;
• at least one die mounted on the interposer substrate;
• a lower pad between the interposer substrate and the package substrate;
• an external terminal between the lower pad and the package substrate;
• an upper pad between the interposer substrate and the at least one die;
• and
• a connection terminal between the upper pad and the at least one die,
• wherein the interposer substrate includes
• a semiconductor substrate having a first surface and a second surface opposite to the first surface, the lower pad on the second surface,
• an etch stop layer on the first surface of the semiconductor substrate,
• an interlayer insulating layer on the etch stop layer,
• a capacitor in a hole penetrating the interlayer insulating layer, wherein a bottom of the hole is distal to the second surface in relation to the first surface based at least in part on the etch stop layer,
• an interconnection layer on the interlayer insulating layer, and
• a through-via extending from the interconnection layer to the lower pad,
• wherein the interconnection layer includes a sequential stack of a plurality of metal layers,
• wherein each metal layer of the plurality of metal layers includes at least one interconnection line and a via vertically overlapping with the at least one interconnection line,
• wherein the upper pad is on an uppermost metal layer of the plurality of metal layers, and
• wherein the capacitor includes a sequential stack, in the hole, of a first electrode, a first dielectric layer, a second electrode, a second dielectric layer and a third electrode.