Memory devices with backside bond pads under a memory array
AssigneeMicron Technology, Inc.
InventorsEric N. Lee, Akira Goda
Life of this patent
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Abstract
An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.
Claims20
An apparatus, comprising:
- a substrate with a frontside and a backside opposite the frontside;
- control circuitry disposed over the frontside of the substrate;
- a memory array disposed over and electrically coupled to the control circuitry;
- a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate;
- and
- a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.
A method for manufacturing a memory die, the method comprising:
- forming a through-silicon via (TSV) in a substrate that has a frontside and a backside opposite the frontside;
- forming control circuitry on the frontside of the substrate;
- forming a memory array over the control circuitry, wherein the memory array is electrically coupled to the control circuitry;
- and
- forming a bond pad on the backside of the substrate, wherein the bond pad is electrically coupled to the control circuitry via the TSV.
An apparatus, comprising:
- a bond pad formed on a backside of a substrate, wherein the substrate has a frontside opposite the backside;
- complementary metal-oxide-semiconductor (CMOS) circuitry disposed over the frontside of the substrate and under a memory array;
- wherein the bond pad is electrically coupled to the CMOS circuitry through a via that passes through the substrate to the CMOS circuitry but does not pass through a plane containing the memory array.
Dependencies are inferred from the claim text.